freedev_vga_hw.tcl

verilog代码读写SDRAM 不带仿真

# TCL File Generated by Component Editor 7.2 on:
# Thu Oct 04 08:10:34 CST 2007
# DO NOT MODIFY

set_source_file "freedev_vga.v"
set_module "freedev_vga"
set_module_description "freefpga's vga control"
set_module_property "author" "www.freefgpa.com"
set_module_property "className" "freedev_vga"
set_module_property "displayName" "freedev_vga"
set_module_property "group" "User Logic"
set_module_property "synthesisFiles" "freedev_vga.v"

# Module parameters
add_parameter "IDLE" "integer" "1" ""
add_parameter "R_START0" "integer" "2" ""
add_parameter "R_START1" "integer" "4" ""
add_parameter "R_DATA" "integer" "8" ""

# Interface clock
add_interface "clock" "clock" "sink" "asynchronous"
# Ports in interface clock
add_port_to_interface "clock" "clk" "clk"
add_port_to_interface "clock" "rst_n" "reset_n"

# Interface export_0
add_interface "export_0" "conduit" "start" "clock"
# Ports in interface export_0
add_port_to_interface "export_0" "pclk" "export"
add_port_to_interface "export_0" "r" "export"
add_port_to_interface "export_0" "g" "export"
add_port_to_interface "export_0" "b" "export"
add_port_to_interface "export_0" "hsync" "export"
add_port_to_interface "export_0" "vsync" "export"
add_port_to_interface "export_0" "blank" "export"
add_port_to_interface "export_0" "sync" "export"
add_port_to_interface "export_0" "psave" "export"

# Interface avalon_slave_0
add_interface "avalon_slave_0" "avalon" "slave" "clock"
set_interface_property "avalon_slave_0" "isNonVolatileStorage" "false"
set_interface_property "avalon_slave_0" "burstOnBurstBoundariesOnly" "false"
set_interface_property "avalon_slave_0" "readLatency" "0"
set_interface_property "avalon_slave_0" "holdTime" "0"
set_interface_property "avalon_slave_0" "printableDevice" "false"
set_interface_property "avalon_slave_0" "readWaitTime" "1"
set_interface_property "avalon_slave_0" "setupTime" "0"
set_interface_property "avalon_slave_0" "addressAlignment" "DYNAMIC"
set_interface_property "avalon_slave_0" "writeWaitTime" "0"
set_interface_property "avalon_slave_0" "timingUnits" "Cycles"
set_interface_property "avalon_slave_0" "minimumUninterruptedRunLength" "1"
set_interface_property "avalon_slave_0" "isMemoryDevice" "false"
set_interface_property "avalon_slave_0" "linewrapBursts" "false"
set_interface_property "avalon_slave_0" "maximumPendingReadTransactions" "0"
# Ports in interface avalon_slave_0
add_port_to_interface "avalon_slave_0" "s_chipselect_n" "chipselect_n"
add_port_to_interface "avalon_slave_0" "s_read_n" "read_n"
add_port_to_interface "avalon_slave_0" "s_write_n" "write_n"
add_port_to_interface "avalon_slave_0" "s_address" "address"
add_port_to_interface "avalon_slave_0" "s_readdata" "readdata"
add_port_to_interface "avalon_slave_0" "s_writedata" "writedata"

# Interface interrupt_sender
add_interface "interrupt_sender" "interrupt" "sender" "clock"
set_interface_property "interrupt_sender" "associatedAddressablePoint" "avalon_slave_0"
# Ports in interface interrupt_sender
add_port_to_interface "interrupt_sender" "s_irq" "irq"

# Interface avalon_master
add_interface "avalon_master" "avalon" "master" "clock"
set_interface_property "avalon_master" "burstOnBurstBoundariesOnly" "false"
set_interface_property "avalon_master" "doStreamReads" "true"
set_interface_property "avalon_master" "linewrapBursts" "false"
set_interface_property "avalon_master" "doStreamWrites" "true"
# Ports in interface avalon_master
add_port_to_interface "avalon_master" "m_waitrequest" "waitrequest"
add_port_to_interface "avalon_master" "m_address" "address"
add_port_to_interface "avalon_master" "m_read" "read"
add_port_to_interface "avalon_master" "m_readdata" "readdata"
add_port_to_interface "avalon_master" "m_write" "write"
add_port_to_interface "avalon_master" "m_writedata" "writedata"
add_port_to_interface "avalon_master" "m_byteenable" "byteenable"
add_port_to_interface "avalon_master" "m_burstcount" "burstcount"
add_port_to_interface "avalon_master" "m_readdatavalid" "readdatavalid"