vga_sys.v

verilog代码读写SDRAM 不带仿真

  always @(posedge clk)
    begin
      if (freedev_vga_inst_avalon_master_requests_burst_0_upstream && (freedev_vga_inst_avalon_master_burstcount == 0) && enable_nonzero_assertions)
        begin
          $write("%0d ns: freedev_vga_inst/avalon_master drove 0 on its 'burstcount' port while accessing slave burst_0/upstream", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burst_0_downstream_arbitrator (
                                       // inputs:
                                        burst_0_downstream_address,
                                        burst_0_downstream_burstcount,
                                        burst_0_downstream_granted_sdram_s1,
                                        burst_0_downstream_qualified_request_sdram_s1,
                                        burst_0_downstream_read,
                                        burst_0_downstream_read_data_valid_sdram_s1,
                                        burst_0_downstream_read_data_valid_sdram_s1_shift_register,
                                        burst_0_downstream_requests_sdram_s1,
                                        burst_0_downstream_write,
                                        burst_0_downstream_writedata,
                                        clk,
                                        d1_sdram_s1_end_xfer,
                                        reset_n,
                                        sdram_s1_readdata_from_sa,
                                        sdram_s1_waitrequest_from_sa,

                                       // outputs:
                                        burst_0_downstream_address_to_slave,
                                        burst_0_downstream_latency_counter,
                                        burst_0_downstream_readdata,
                                        burst_0_downstream_readdatavalid,
                                        burst_0_downstream_reset_n,
                                        burst_0_downstream_waitrequest
                                     )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [ 25: 0] burst_0_downstream_address_to_slave;
  output           burst_0_downstream_latency_counter;
  output  [ 15: 0] burst_0_downstream_readdata;
  output           burst_0_downstream_readdatavalid;
  output           burst_0_downstream_reset_n;
  output           burst_0_downstream_waitrequest;
  input   [ 25: 0] burst_0_downstream_address;
  input            burst_0_downstream_burstcount;
  input            burst_0_downstream_granted_sdram_s1;
  input            burst_0_downstream_qualified_request_sdram_s1;
  input            burst_0_downstream_read;
  input            burst_0_downstream_read_data_valid_sdram_s1;
  input            burst_0_downstream_read_data_valid_sdram_s1_shift_register;
  input            burst_0_downstream_requests_sdram_s1;
  input            burst_0_downstream_write;
  input   [ 15: 0] burst_0_downstream_writedata;
  input            clk;
  input            d1_sdram_s1_end_xfer;
  input            reset_n;
  input   [ 15: 0] sdram_s1_readdata_from_sa;
  input            sdram_s1_waitrequest_from_sa;

  reg              active_and_waiting_last_time;
  reg     [ 25: 0] burst_0_downstream_address_last_time;
  wire    [ 25: 0] burst_0_downstream_address_to_slave;
  reg              burst_0_downstream_burstcount_last_time;
  wire             burst_0_downstream_is_granted_some_slave;
  reg              burst_0_downstream_latency_counter;
  reg              burst_0_downstream_read_but_no_slave_selected;
  reg              burst_0_downstream_read_last_time;
  wire    [ 15: 0] burst_0_downstream_readdata;
  wire             burst_0_downstream_readdatavalid;
  wire             burst_0_downstream_reset_n;
  wire             burst_0_downstream_run;
  wire             burst_0_downstream_waitrequest;
  reg              burst_0_downstream_write_last_time;
  reg     [ 15: 0] burst_0_downstream_writedata_last_time;
  wire             latency_load_value;
  wire             p1_burst_0_downstream_latency_counter;
  wire             pre_flush_burst_0_downstream_readdatavalid;
  wire             r_0;
  wire             r_1;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (burst_0_downstream_qualified_request_sdram_s1 | ~burst_0_downstream_requests_sdram_s1) & (burst_0_downstream_granted_sdram_s1 | ~burst_0_downstream_qualified_request_sdram_s1) & ((~burst_0_downstream_qualified_request_sdram_s1 | ~(burst_0_downstream_read | burst_0_downstream_write) | (1 & ~sdram_s1_waitrequest_from_sa & (burst_0_downstream_read | burst_0_downstream_write))));

  //cascaded wait assignment, which is an e_assign
  assign burst_0_downstream_run = r_0 & r_1;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = ~burst_0_downstream_qualified_request_sdram_s1 | ~(burst_0_downstream_read | burst_0_downstream_write) | (1 & ~sdram_s1_waitrequest_from_sa & (burst_0_downstream_read | burst_0_downstream_write));

  //optimize select-logic by passing only those address bits which matter.
  assign burst_0_downstream_address_to_slave = burst_0_downstream_address;

  //burst_0_downstream_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_downstream_read_but_no_slave_selected <= 0;
      else if (1)
          burst_0_downstream_read_but_no_slave_selected <= burst_0_downstream_read & burst_0_downstream_run & ~burst_0_downstream_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign burst_0_downstream_is_granted_some_slave = burst_0_downstream_granted_sdram_s1;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_burst_0_downstream_readdatavalid = burst_0_downstream_read_data_valid_sdram_s1;

  //latent slave read data valid which is not flushed, which is an e_mux
  assign burst_0_downstream_readdatavalid = burst_0_downstream_read_but_no_slave_selected |
    pre_flush_burst_0_downstream_readdatavalid;

  //burst_0/downstream readdata mux, which is an e_mux
  assign burst_0_downstream_readdata = sdram_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign burst_0_downstream_waitrequest = ~burst_0_downstream_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_downstream_latency_counter <= 0;
      else if (1)
          burst_0_downstream_latency_counter <= p1_burst_0_downstream_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_burst_0_downstream_latency_counter = ((burst_0_downstream_run & burst_0_downstream_read))? latency_load_value :
    (burst_0_downstream_latency_counter)? burst_0_downstream_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = 0;

  //burst_0_downstream_reset_n assignment, which is an e_assign
  assign burst_0_downstream_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //burst_0_downstream_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_downstream_address_last_time <= 0;
      else if (1)
          burst_0_downstream_address_last_time <= burst_0_downstream_address;
    end


  //burst_0/downstream waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else if (1)
          active_and_waiting_last_time <= burst_0_downstream_waitrequest & (burst_0_downstream_read | burst_0_downstream_write);
    end


  //burst_0_downstream_address matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or burst_0_downstream_address or burst_0_downstream_address_last_time)
    begin
      if (active_and_waiting_last_time & (burst_0_downstream_address != burst_0_downstream_address_last_time))
        begin
          $write("%0d ns: burst_0_downstream_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //burst_0_downstream_burstcount check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_downstream_burstcount_last_time <= 0;
      else if (1)
          burst_0_downstream_burstcount_last_time <= burst_0_downstream_burstcount;
    end


  //burst_0_downstream_burstcount matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or burst_0_downstream_burstcount or burst_0_downstream_burstcount_last_time)
    begin
      if (active_and_waiting_last_time & (burst_0_downstream_burstcount != burst_0_downstream_burstcount_last_time))
        begin
          $write("%0d ns: burst_0_downstream_burstcount did not heed wait!!!", $time);
          $stop;
        end
    end


  //burst_0_downstream_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_downstream_read_last_time <= 0;
      else if (1)
          burst_0_downstream_read_last_time <= burst_0_downstream_read;
    end


  //burst_0_downstream_read matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or burst_0_downstream_read or burst_0_downstream_read_last_time)
    begin
      if (active_and_waiting_last_time & (burst_0_downstream_read != burst_0_downstream_read_last_time))
        begin
          $write("%0d ns: burst_0_downstream_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //burst_0_downstream_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_downstream_write_last_time <= 0;
      else if (1)
          burst_0_downstream_write_last_time <= burst_0_downstream_write;
    end


  //burst_0_downstream_write matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or burst_0_downstream_write or burst_0_downstream_write_last_time)
    begin
      if (active_and_waiting_last_time & (burst_0_downstream_write != burst_0_downstream_write_last_time))
        begin
          $write("%0d ns: burst_0_downstream_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //burst_0_downstream_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_downstream_writedata_last_time <= 0;
      else if (1)
          burst_0_downstream_writedata_last_time <= burst_0_downstream_writedata;
    end


  //burst_0_downstream_writedata matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or burst_0_downstream_write or burst_0_downstream_writedata or burst_0_downstream_writedata_last_time)
    begin
      if (active_and_waiting_last_time & (burst_0_downstream_writedata != burst_0_downstream_writedata_last_time) & burst_0_downstream_write)
        begin
          $write("%0d ns: burst_0_downstream_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_jtag_debug_module_arbitrator (
                                          // inputs:
                                           clk,
                                           cpu_data_master_address_to_slave,
                                           cpu_data_master_byteenable,
                                           cpu_data_master_debugaccess,
                                           cpu_data_master_latency_counter,
                                           cpu_data_master_read,
                                           cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                           cpu_data_master_write,
                                           cpu_data_master_writedata,
                                           cpu_instruction_master_address_to_slave,
                                           cpu_instruction_master_latency_counter,
                                           cpu_instruction_master_read,
                                           cpu_instruction_master_read_data_valid_sdram_s1_shift_register,
                                           cpu_jtag_debug_module_readdata,
                                           cpu_jtag_debug_module_resetrequest,
                                           reset_n,

                                          // outputs:
                                           cpu_data_master_granted_cpu_jtag_debug_module,
                                           cpu_data_master_qualified_request_cpu_jtag_debug_module,
                                           cpu_data_master_read_data_valid_cpu_jtag_debug_module,
                                           cpu_data_master_requests_cpu_jtag_debug_module,
                                           cpu_instruction_master_granted_cpu_jtag_debug_module,
                                           cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
                                           cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
                                           cpu_instruction_master_requests_cpu_jtag_debug_module,
                                           cpu_jtag_debug_module_address,
                                           cpu_jtag_debug_module_begintransfer,
                                           cpu_jtag_debug_module_byteenable,
                                           cpu_jtag_debug_module_chipselect,
                                           cpu_jtag_debug_module_debugaccess,
                                           cpu_jtag_debug_module_readdata_from_sa,
                                           cpu_jtag_debug_module_reset,
                                           cpu_jtag_de