vga_sys.v

verilog代码读写SDRAM 不带仿真

  wire    [  8: 0] burst_0_upstream_next_burst_count;
  wire             burst_0_upstream_non_bursting_master_requests;
  wire             burst_0_upstream_read;
  wire    [ 15: 0] burst_0_upstream_readdata_from_sa;
  wire             burst_0_upstream_readdatavalid_from_sa;
  reg              burst_0_upstream_reg_firsttransfer;
  wire    [  8: 0] burst_0_upstream_selected_burstcount;
  reg              burst_0_upstream_slavearbiterlockenable;
  wire             burst_0_upstream_slavearbiterlockenable2;
  wire             burst_0_upstream_this_cycle_is_the_last_burst;
  wire    [  8: 0] burst_0_upstream_transaction_burst_count;
  wire             burst_0_upstream_unreg_firsttransfer;
  wire             burst_0_upstream_waitrequest_from_sa;
  wire             burst_0_upstream_waits_for_read;
  wire             burst_0_upstream_waits_for_write;
  wire             burst_0_upstream_write;
  wire    [ 15: 0] burst_0_upstream_writedata;
  reg              d1_burst_0_upstream_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_burst_0_upstream;
  wire             freedev_vga_inst_avalon_master_arbiterlock;
  wire             freedev_vga_inst_avalon_master_arbiterlock2;
  wire    [  1: 0] freedev_vga_inst_avalon_master_byteenable_burst_0_upstream;
  wire    [  1: 0] freedev_vga_inst_avalon_master_byteenable_burst_0_upstream_segment_0;
  wire    [  1: 0] freedev_vga_inst_avalon_master_byteenable_burst_0_upstream_segment_1;
  wire             freedev_vga_inst_avalon_master_continuerequest;
  wire             freedev_vga_inst_avalon_master_granted_burst_0_upstream;
  wire             freedev_vga_inst_avalon_master_qualified_request_burst_0_upstream;
  wire             freedev_vga_inst_avalon_master_rdv_fifo_empty_burst_0_upstream;
  wire             freedev_vga_inst_avalon_master_rdv_fifo_output_from_burst_0_upstream;
  wire             freedev_vga_inst_avalon_master_read_data_valid_burst_0_upstream;
  wire             freedev_vga_inst_avalon_master_read_data_valid_burst_0_upstream_shift_register;
  wire             freedev_vga_inst_avalon_master_requests_burst_0_upstream;
  wire             freedev_vga_inst_avalon_master_saved_grant_burst_0_upstream;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p0_burst_0_upstream_load_fifo;
  wire             wait_for_burst_0_upstream_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~burst_0_upstream_end_xfer;
    end


  assign burst_0_upstream_begins_xfer = ~d1_reasons_to_wait & ((freedev_vga_inst_avalon_master_qualified_request_burst_0_upstream));
  //assign burst_0_upstream_readdata_from_sa = burst_0_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign burst_0_upstream_readdata_from_sa = burst_0_upstream_readdata;

  assign freedev_vga_inst_avalon_master_requests_burst_0_upstream = ({freedev_vga_inst_avalon_master_address_to_slave[31 : 26] , 26'b0} == 32'h8000000) & (freedev_vga_inst_avalon_master_read | freedev_vga_inst_avalon_master_write);
  //assign burst_0_upstream_waitrequest_from_sa = burst_0_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign burst_0_upstream_waitrequest_from_sa = burst_0_upstream_waitrequest;

  //assign burst_0_upstream_readdatavalid_from_sa = burst_0_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign burst_0_upstream_readdatavalid_from_sa = burst_0_upstream_readdatavalid;

  //burst_0_upstream_arb_share_counter set values, which is an e_mux
  assign burst_0_upstream_arb_share_set_values = (freedev_vga_inst_avalon_master_granted_burst_0_upstream)? (((freedev_vga_inst_avalon_master_write) ? freedev_vga_inst_avalon_master_burstcount<< 1 : 1)) :
    1;

  //burst_0_upstream_non_bursting_master_requests mux, which is an e_mux
  assign burst_0_upstream_non_bursting_master_requests = 0;

  //burst_0_upstream_any_bursting_master_saved_grant mux, which is an e_mux
  assign burst_0_upstream_any_bursting_master_saved_grant = freedev_vga_inst_avalon_master_saved_grant_burst_0_upstream;

  //burst_0_upstream_arb_share_counter_next_value assignment, which is an e_assign
  assign burst_0_upstream_arb_share_counter_next_value = burst_0_upstream_firsttransfer ? (burst_0_upstream_arb_share_set_values - 1) : |burst_0_upstream_arb_share_counter ? (burst_0_upstream_arb_share_counter - 1) : 0;

  //burst_0_upstream_allgrants all slave grants, which is an e_mux
  assign burst_0_upstream_allgrants = |burst_0_upstream_grant_vector;

  //burst_0_upstream_end_xfer assignment, which is an e_assign
  assign burst_0_upstream_end_xfer = ~(burst_0_upstream_waits_for_read | burst_0_upstream_waits_for_write);

  //end_xfer_arb_share_counter_term_burst_0_upstream arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_burst_0_upstream = burst_0_upstream_end_xfer & (~burst_0_upstream_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //burst_0_upstream_arb_share_counter arbitration counter enable, which is an e_assign
  assign burst_0_upstream_arb_counter_enable = (end_xfer_arb_share_counter_term_burst_0_upstream & burst_0_upstream_allgrants) | (end_xfer_arb_share_counter_term_burst_0_upstream & ~burst_0_upstream_non_bursting_master_requests);

  //burst_0_upstream_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_upstream_arb_share_counter <= 0;
      else if (burst_0_upstream_arb_counter_enable)
          burst_0_upstream_arb_share_counter <= burst_0_upstream_arb_share_counter_next_value;
    end


  //burst_0_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_upstream_slavearbiterlockenable <= 0;
      else if ((|burst_0_upstream_master_qreq_vector & end_xfer_arb_share_counter_term_burst_0_upstream) | (end_xfer_arb_share_counter_term_burst_0_upstream & ~burst_0_upstream_non_bursting_master_requests))
          burst_0_upstream_slavearbiterlockenable <= |burst_0_upstream_arb_share_counter_next_value;
    end


  //freedev_vga_inst/avalon_master burst_0/upstream arbiterlock, which is an e_assign
  assign freedev_vga_inst_avalon_master_arbiterlock = burst_0_upstream_slavearbiterlockenable & freedev_vga_inst_avalon_master_continuerequest;

  //burst_0_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign burst_0_upstream_slavearbiterlockenable2 = |burst_0_upstream_arb_share_counter_next_value;

  //freedev_vga_inst/avalon_master burst_0/upstream arbiterlock2, which is an e_assign
  assign freedev_vga_inst_avalon_master_arbiterlock2 = burst_0_upstream_slavearbiterlockenable2 & freedev_vga_inst_avalon_master_continuerequest;

  //burst_0_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
  assign burst_0_upstream_any_continuerequest = 1;

  //freedev_vga_inst_avalon_master_continuerequest continued request, which is an e_assign
  assign freedev_vga_inst_avalon_master_continuerequest = 1;

  assign freedev_vga_inst_avalon_master_qualified_request_burst_0_upstream = freedev_vga_inst_avalon_master_requests_burst_0_upstream & ~((freedev_vga_inst_avalon_master_read & ((freedev_vga_inst_avalon_master_latency_counter != 0) | (1 < freedev_vga_inst_avalon_master_latency_counter))));
  //unique name for burst_0_upstream_move_on_to_next_transaction, which is an e_assign
  assign burst_0_upstream_move_on_to_next_transaction = burst_0_upstream_this_cycle_is_the_last_burst & burst_0_upstream_load_fifo;

  //the currently selected burstcount for burst_0_upstream, which is an e_mux
  assign burst_0_upstream_selected_burstcount = (freedev_vga_inst_avalon_master_granted_burst_0_upstream)? freedev_vga_inst_avalon_master_burstcount :
    1;

  //burstcount_fifo_for_burst_0_upstream, which is an e_fifo_with_registered_outputs
  burstcount_fifo_for_burst_0_upstream_module burstcount_fifo_for_burst_0_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (burst_0_upstream_selected_burstcount),
      .data_out             (burst_0_upstream_transaction_burst_count),
      .empty                (burst_0_upstream_burstcount_fifo_empty),
      .fifo_contains_ones_n (),
      .full                 (),
      .read                 (burst_0_upstream_this_cycle_is_the_last_burst),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~burst_0_upstream_waits_for_read & burst_0_upstream_load_fifo & ~(burst_0_upstream_this_cycle_is_the_last_burst & burst_0_upstream_burstcount_fifo_empty))
    );

  //burst_0_upstream current burst minus one, which is an e_assign
  assign burst_0_upstream_current_burst_minus_one = burst_0_upstream_current_burst - 1;

  //what to load in current_burst, for burst_0_upstream, which is an e_mux
  assign burst_0_upstream_next_burst_count = (((in_a_read_cycle & ~burst_0_upstream_waits_for_read) & ~burst_0_upstream_load_fifo))? {burst_0_upstream_selected_burstcount, 1'b0} :
    ((in_a_read_cycle & ~burst_0_upstream_waits_for_read & burst_0_upstream_this_cycle_is_the_last_burst & burst_0_upstream_burstcount_fifo_empty))? {burst_0_upstream_selected_burstcount, 1'b0} :
    (burst_0_upstream_this_cycle_is_the_last_burst)? {burst_0_upstream_transaction_burst_count,  1'b0} :
    burst_0_upstream_current_burst_minus_one;

  //the current burst count for burst_0_upstream, to be decremented, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_upstream_current_burst <= 0;
      else if (burst_0_upstream_readdatavalid_from_sa | (~burst_0_upstream_load_fifo & (in_a_read_cycle & ~burst_0_upstream_waits_for_read)))
          burst_0_upstream_current_burst <= burst_0_upstream_next_burst_count;
    end


  //a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
  assign p0_burst_0_upstream_load_fifo = (~burst_0_upstream_load_fifo)? 1 :
    (((in_a_read_cycle & ~burst_0_upstream_waits_for_read) & burst_0_upstream_load_fifo))? 1 :
    ~burst_0_upstream_burstcount_fifo_empty;

  //whether to load directly to the counter or to the fifo, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_upstream_load_fifo <= 0;
      else if ((in_a_read_cycle & ~burst_0_upstream_waits_for_read) & ~burst_0_upstream_load_fifo | burst_0_upstream_this_cycle_is_the_last_burst)
          burst_0_upstream_load_fifo <= p0_burst_0_upstream_load_fifo;
    end


  //the last cycle in the burst for burst_0_upstream, which is an e_assign
  assign burst_0_upstream_this_cycle_is_the_last_burst = ~(|burst_0_upstream_current_burst_minus_one) & burst_0_upstream_readdatavalid_from_sa;

  //rdv_fifo_for_freedev_vga_inst_avalon_master_to_burst_0_upstream, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_freedev_vga_inst_avalon_master_to_burst_0_upstream_module rdv_fifo_for_freedev_vga_inst_avalon_master_to_burst_0_upstream
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (freedev_vga_inst_avalon_master_granted_burst_0_upstream),
      .data_out             (freedev_vga_inst_avalon_master_rdv_fifo_output_from_burst_0_upstream),
      .empty                (),
      .fifo_contains_ones_n (freedev_vga_inst_avalon_master_rdv_fifo_empty_burst_0_upstream),
      .full                 (),
      .read                 (burst_0_upstream_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~burst_0_upstream_waits_for_read)
    );

  assign freedev_vga_inst_avalon_master_read_data_valid_burst_0_upstream_shift_register = ~freedev_vga_inst_avalon_master_rdv_fifo_empty_burst_0_upstream;
  //local readdatavalid freedev_vga_inst_avalon_master_read_data_valid_burst_0_upstream, which is an e_mux
  assign freedev_vga_inst_avalon_master_read_data_valid_burst_0_upstream = burst_0_upstream_readdatavalid_from_sa;

  //burst_0_upstream_writedata mux, which is an e_mux
  assign burst_0_upstream_writedata = freedev_vga_inst_avalon_master_dbs_write_16;

  //byteaddress mux for burst_0/upstream, which is an e_mux
  assign burst_0_upstream_byteaddress = freedev_vga_inst_avalon_master_address_to_slave;

  //master is always granted when requested
  assign freedev_vga_inst_avalon_master_granted_burst_0_upstream = freedev_vga_inst_avalon_master_qualified_request_burst_0_upstream;

  //freedev_vga_inst/avalon_master saved-grant burst_0/upstream, which is an e_assign
  assign freedev_vga_inst_avalon_master_saved_grant_burst_0_upstream = freedev_vga_inst_avalon_master_requests_burst_0_upstream;

  //allow new arb cycle for burst_0/upstream, which is an e_assign
  assign burst_0_upstream_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign burst_0_upstream_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign burst_0_upstream_master_qreq_vector = 1;

  //burst_0_upstream_firsttransfer first transaction, which is an e_assign
  assign burst_0_upstream_firsttransfer = burst_0_upstream_begins_xfer ? burst_0_upstream_unreg_firsttransfer : burst_0_upstream_reg_firsttransfer;

  //burst_0_upstream_unreg_firsttransfer first transaction, which is an e_assign
  assign burst_0_upstream_unreg_firsttransfer = ~(burst_0_upstream_slavearbiterlockenable & burst_0_upstream_any_continuerequest);

  //burst_0_upstream_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_upstream_reg_firsttransfer <= 1'b1;
      else if (burst_0_upstream_begins_xfer)
          burst_0_upstream_reg_firsttransfer <= burst_0_upstream_unreg_firsttransfer;
    end


  //burst_0_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
  assign burst_0_upstream_next_bbt_burstcount = ((((burst_0_upstream_write) && (burst_0_upstream_bbt_burstcounter == 0))))? (burst_0_upstream_burstcount - 1) :
    ((((burst_0_upstream_read) && (burst_0_upstream_bbt_burstcounter == 0))))? 0 :
    (burst_0_upstream_bbt_burstcounter - 1);

  //burst_0_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          burst_0_upstream_bbt_burstcounter <= 0;
      else if (burst_0_upstream_begins_xfer)
          burst_0_upstream_bbt_burstcounter <= burst_0_upstream_next_bbt_burstcount;
    end


  //burst_0_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign burst_0_upstream_beginbursttransfer_internal = burst_0_upstream_begins_xfer & (burst_0_upstream_bbt_burstcounter == 0);

  //burst_0_upstream_read assignment, which is an e_mux
  assign burst_0_upstream_read = freedev_vga_inst_avalon_master_granted_burst_0_upstream & freedev_vga_inst_avalon_master_read;

  //burst_0_upstream_write assignment, which is an e_mux
  assign burst_0_upstream_write = freedev_vga_inst_avalon_master_granted_burst_0_upstream & freedev_vga_inst_avalon_master_write;

  //burst_0_upstream_address mux, which is an e_mux
  assign burst_0_upstream_address = {freedev_vga_inst_avalon_master_address_to_slave >> 2,
    freedev_vga_inst_avalon_master_dbs_address[1],
    {1 {1'b0}}};

  //d1_burst_0_upstream_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_burst_0_upstream_end_xfer <= 1;
      else if (1)
          d1_burst_0_upstream_end_xfer <= burst_0_upstream_end_xfer;
    end


  //burst_0_upstream_waits_for_read in a cycle, which is an e_mux
  assign burst_0_upstream_waits_for_read = burst_0_upstream_in_a_read_cycle & burst_0_upstream_waitrequest_from_sa;

  //burst_0_upstream_in_a_read_cycle assignment, which is an e_assign
  assign burst_0_upstream_in_a_read_cycle = freedev_vga_inst_avalon_master_granted_burst_0_upstream & freedev_vga_inst_avalon_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = burst_0_upstream_in_a_read_cycle;

  //burst_0_upstream_waits_for_write in a cycle, which is an e_mux
  assign burst_0_upstream_waits_for_write = burst_0_upstream_in_a_write_cycle & burst_0_upstream_waitrequest_from_sa;

  //burst_0_upstream_in_a_write_cycle assignment, which is an e_assign
  assign burst_0_upstream_in_a_write_cycle = freedev_vga_inst_avalon_master_granted_burst_0_upstream & freedev_vga_inst_avalon_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = burst_0_upstream_in_a_write_cycle;

  assign wait_for_burst_0_upstream_counter = 0;
  //burst_0_upstream_byteenable byte enable port mux, which is an e_mux
  assign burst_0_upstream_byteenable = (freedev_vga_inst_avalon_master_granted_burst_0_upstream)? freedev_vga_inst_avalon_master_byteenable_burst_0_upstream :
    -1;

  assign {freedev_vga_inst_avalon_master_byteenable_burst_0_upstream_segment_1,
freedev_vga_inst_avalon_master_byteenable_burst_0_upstream_segment_0} = freedev_vga_inst_avalon_master_byteenable;
  assign freedev_vga_inst_avalon_master_byteenable_burst_0_upstream = ((freedev_vga_inst_avalon_master_dbs_address[1] == 0))? freedev_vga_inst_avalon_master_byteenable_burst_0_upstream_segment_0 :
    freedev_vga_inst_avalon_master_byteenable_burst_0_upstream_segment_1;

  //burstcount mux, which is an e_mux
  assign burst_0_upstream_burstcount = (freedev_vga_inst_avalon_master_granted_burst_0_upstream)? freedev_vga_inst_avalon_master_burstcount :
    1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //burst_0/upstream enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end


  //freedev_vga_inst/avalon_master non-zero burstcount assertion, which is an e_process