vga_sys.v

verilog代码读写SDRAM 不带仿真

    end


  //control_5, which is an e_mux
  assign p5_full_5 = ((read & !write) == 0)? full_4 :
    full_6;

  //control_reg_5, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_5 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_5 <= 0;
          else 
            full_5 <= p5_full_5;
    end


  //data_4, which is an e_mux
  assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
    stage_5;

  //data_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_4 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_4))
          if (sync_reset & full_4 & !((full_5 == 0) & read & write))
              stage_4 <= 0;
          else 
            stage_4 <= p4_stage_4;
    end


  //control_4, which is an e_mux
  assign p4_full_4 = ((read & !write) == 0)? full_3 :
    full_5;

  //control_reg_4, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_4 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_4 <= 0;
          else 
            full_4 <= p4_full_4;
    end


  //data_3, which is an e_mux
  assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
    stage_4;

  //data_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_3 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_3))
          if (sync_reset & full_3 & !((full_4 == 0) & read & write))
              stage_3 <= 0;
          else 
            stage_3 <= p3_stage_3;
    end


  //control_3, which is an e_mux
  assign p3_full_3 = ((read & !write) == 0)? full_2 :
    full_4;

  //control_reg_3, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module burst_0_upstream_arbitrator (
                                     // inputs:
                                      burst_0_upstream_readdata,
                                      burst_0_upstream_readdatavalid,
                                      burst_0_upstream_waitrequest,
                                      clk,
                                      freedev_vga_inst_avalon_master_address_to_slave,
                                      freedev_vga_inst_avalon_master_burstcount,
                                      freedev_vga_inst_avalon_master_byteenable,
                                      freedev_vga_inst_avalon_master_dbs_address,
                                      freedev_vga_inst_avalon_master_dbs_write_16,
                                      freedev_vga_inst_avalon_master_latency_counter,
                                      freedev_vga_inst_avalon_master_read,
                                      freedev_vga_inst_avalon_master_write,
                                      reset_n,

                                     // outputs:
                                      burst_0_upstream_address,
                                      burst_0_upstream_burstcount,
                                      burst_0_upstream_byteaddress,
                                      burst_0_upstream_byteenable,
                                      burst_0_upstream_read,
                                      burst_0_upstream_readdata_from_sa,
                                      burst_0_upstream_waitrequest_from_sa,
                                      burst_0_upstream_write,
                                      burst_0_upstream_writedata,
                                      d1_burst_0_upstream_end_xfer,
                                      freedev_vga_inst_avalon_master_byteenable_burst_0_upstream,
                                      freedev_vga_inst_avalon_master_granted_burst_0_upstream,
                                      freedev_vga_inst_avalon_master_qualified_request_burst_0_upstream,
                                      freedev_vga_inst_avalon_master_read_data_valid_burst_0_upstream,
                                      freedev_vga_inst_avalon_master_read_data_valid_burst_0_upstream_shift_register,
                                      freedev_vga_inst_avalon_master_requests_burst_0_upstream
                                   )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [ 25: 0] burst_0_upstream_address;
  output  [  7: 0] burst_0_upstream_burstcount;
  output  [ 26: 0] burst_0_upstream_byteaddress;
  output  [  1: 0] burst_0_upstream_byteenable;
  output           burst_0_upstream_read;
  output  [ 15: 0] burst_0_upstream_readdata_from_sa;
  output           burst_0_upstream_waitrequest_from_sa;
  output           burst_0_upstream_write;
  output  [ 15: 0] burst_0_upstream_writedata;
  output           d1_burst_0_upstream_end_xfer;
  output  [  1: 0] freedev_vga_inst_avalon_master_byteenable_burst_0_upstream;
  output           freedev_vga_inst_avalon_master_granted_burst_0_upstream;
  output           freedev_vga_inst_avalon_master_qualified_request_burst_0_upstream;
  output           freedev_vga_inst_avalon_master_read_data_valid_burst_0_upstream;
  output           freedev_vga_inst_avalon_master_read_data_valid_burst_0_upstream_shift_register;
  output           freedev_vga_inst_avalon_master_requests_burst_0_upstream;
  input   [ 15: 0] burst_0_upstream_readdata;
  input            burst_0_upstream_readdatavalid;
  input            burst_0_upstream_waitrequest;
  input            clk;
  input   [ 31: 0] freedev_vga_inst_avalon_master_address_to_slave;
  input   [  7: 0] freedev_vga_inst_avalon_master_burstcount;
  input   [  3: 0] freedev_vga_inst_avalon_master_byteenable;
  input   [  1: 0] freedev_vga_inst_avalon_master_dbs_address;
  input   [ 15: 0] freedev_vga_inst_avalon_master_dbs_write_16;
  input            freedev_vga_inst_avalon_master_latency_counter;
  input            freedev_vga_inst_avalon_master_read;
  input            freedev_vga_inst_avalon_master_write;
  input            reset_n;

  wire    [ 25: 0] burst_0_upstream_address;
  wire             burst_0_upstream_allgrants;
  wire             burst_0_upstream_allow_new_arb_cycle;
  wire             burst_0_upstream_any_bursting_master_saved_grant;
  wire             burst_0_upstream_any_continuerequest;
  wire             burst_0_upstream_arb_counter_enable;
  reg     [  9: 0] burst_0_upstream_arb_share_counter;
  wire    [  9: 0] burst_0_upstream_arb_share_counter_next_value;
  wire    [  9: 0] burst_0_upstream_arb_share_set_values;
  reg     [  6: 0] burst_0_upstream_bbt_burstcounter;
  wire             burst_0_upstream_beginbursttransfer_internal;
  wire             burst_0_upstream_begins_xfer;
  wire    [  7: 0] burst_0_upstream_burstcount;
  wire             burst_0_upstream_burstcount_fifo_empty;
  wire    [ 26: 0] burst_0_upstream_byteaddress;
  wire    [  1: 0] burst_0_upstream_byteenable;
  reg     [  8: 0] burst_0_upstream_current_burst;
  wire    [  8: 0] burst_0_upstream_current_burst_minus_one;
  wire             burst_0_upstream_end_xfer;
  wire             burst_0_upstream_firsttransfer;
  wire             burst_0_upstream_grant_vector;
  wire             burst_0_upstream_in_a_read_cycle;
  wire             burst_0_upstream_in_a_write_cycle;
  reg              burst_0_upstream_load_fifo;
  wire             burst_0_upstream_master_qreq_vector;
  wire             burst_0_upstream_move_on_to_next_transaction;
  wire    [  6: 0] burst_0_upstream_next_bbt_burstcount;