📄 lp_dma_dsp_b.c
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// Link port DMA in C using builtin functions
#include "sysreg.h"
#include "signal.h"
#include "stdio.h"
#include <defts201.h>
#define N 64 // Number of words to transfer
float dm buffer[N]; // Buffer for received data and for transmitting back
struct TCB {
float *DI; // index
int DX; // count and stride in x direction
int DY; // count and stride in y direction
int DP; // DMA control word
};
struct TCB TCB_temp; // Temp structure for programming TCBs
__builtin_quad q; // Temp quad for programming TCBs
void isr_DMA6(int); // Protos for isr's
void isr_DMA10(int);
void main(void)
{
int i;
volatile int k; // loop var
interrupt(SIGDMA6, isr_DMA6); // Assign isr to DMA channel 6
interrupt(SIGDMA10, isr_DMA10); // Assign isr to DMA channel 10
TCB_temp.DI = buffer; // index points to destination buffer
TCB_temp.DX = 4 | (N << 16); // modify is 4 for quad-word transfers, count is N and must be shifted to upper half
TCB_temp.DY = 0; // only a 1 dimension DMA
TCB_temp.DP = 0x47000000; // control word set for quad-word transfers to internal memory with interrupt enabled
__builtin_sysreg_write(__LTCTL2,0x1); // setup LP2 to transmit
__builtin_sysreg_write(__LRCTL2,0x1); // and also setup LP2 to receive
//******************************************************************************
/* Following lines of code insert a wait time of (75000 * LxCLKO_period) between
link transmit port and due to
a silicon anomaly on ADSP-TS201. Please refer TigerSHARC anomaly list (revisions
1.0 and 1.1) for more details */
//******************************************************************************
for (i=0;i<75000;i++)
k=i+1;
q = __builtin_compose_128((long long)TCB_temp.DI | (long long)TCB_temp.DX << 32, (long long)(TCB_temp.DY | (long long)TCB_temp.DP << 32));
__builtin_sysreg_write4(__DC10, q); // program the TCBs
while(1) // Endless loop
i=i-i;
}
void isr_DMA10(int dummy) // isr for DMA channel 10, sets up DMA channel 6 to transmit buffer back
{
TCB_temp.DI = buffer; // index points to buffer
TCB_temp.DP = 0x47000000; // control word set for quad-word transfers to internal memory with interrupt enabled
q = __builtin_compose_128((long long)TCB_temp.DI | (long long)TCB_temp.DX << 32, (long long)(TCB_temp.DY | (long long)TCB_temp.DP << 32));
__builtin_sysreg_write4(__DC6, q); // program the TCBs
return;
}
void isr_DMA6(int dummy) // isr for DMA channel 6
{
printf("LP DMAs Complete\n");
return;
}
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