lcd.rpt

这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,

	clkdiv(5) AND clkdiv(6) AND clkdiv(7) AND clkdiv(8) AND clkdiv(9));

FTCPE_clkdiv18: FTCPE port map (clkdiv(18),clkdiv_T(18),clk,Reset,'0');
clkdiv_T(18) <= (clkdiv(0) AND clkdiv(10) AND clkdiv(11) AND 
	clkdiv(12) AND clkdiv(13) AND clkdiv(14) AND clkdiv(15) AND 
	clkdiv(16) AND clkdiv(17) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND 
	clkdiv(4) AND clkdiv(5) AND clkdiv(6) AND clkdiv(7) AND clkdiv(8) AND 
	clkdiv(9));

FTCPE_clkdiv19: FTCPE port map (clkdiv(19),clkdiv_T(19),clk,Reset,'0');
clkdiv_T(19) <= (clkdiv(0) AND clkdiv(10) AND clkdiv(11) AND 
	clkdiv(12) AND clkdiv(13) AND clkdiv(14) AND clkdiv(15) AND 
	clkdiv(16) AND clkdiv(17) AND clkdiv(18) AND clkdiv(1) AND clkdiv(2) AND 
	clkdiv(3) AND clkdiv(4) AND clkdiv(5) AND clkdiv(6) AND clkdiv(7) AND 
	clkdiv(8) AND clkdiv(9));

FTCPE_clkdiv1: FTCPE port map (clkdiv(1),clkdiv(0),clk,Reset,'0');

FTCPE_clkdiv20: FTCPE port map (clkdiv(20),clkdiv_T(20),clk,Reset,'0');
clkdiv_T(20) <= (clkdiv(0) AND clkdiv(10) AND clkdiv(11) AND 
	clkdiv(12) AND clkdiv(13) AND clkdiv(14) AND clkdiv(15) AND 
	clkdiv(16) AND clkdiv(17) AND clkdiv(18) AND clkdiv(19) AND 
	clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND clkdiv(4) AND clkdiv(5) AND 
	clkdiv(6) AND clkdiv(7) AND clkdiv(8) AND clkdiv(9));

FTCPE_clkdiv21: FTCPE port map (clkdiv(21),clkdiv_T(21),clk,Reset,'0');
clkdiv_T(21) <= (clkdiv(0) AND clkdiv(20) AND clkdiv(10) AND 
	clkdiv(11) AND clkdiv(12) AND clkdiv(13) AND clkdiv(14) AND 
	clkdiv(15) AND clkdiv(16) AND clkdiv(17) AND clkdiv(18) AND 
	clkdiv(19) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND clkdiv(4) AND 
	clkdiv(5) AND clkdiv(6) AND clkdiv(7) AND clkdiv(8) AND clkdiv(9));

FTCPE_clkdiv22: FTCPE port map (clkdiv(22),clkdiv_T(22),clk,Reset,'0');
clkdiv_T(22) <= (clkdiv(0) AND clkdiv(20) AND clkdiv(21) AND 
	clkdiv(10) AND clkdiv(11) AND clkdiv(12) AND clkdiv(13) AND 
	clkdiv(14) AND clkdiv(15) AND clkdiv(16) AND clkdiv(17) AND 
	clkdiv(18) AND clkdiv(19) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND 
	clkdiv(4) AND clkdiv(5) AND clkdiv(6) AND clkdiv(7) AND clkdiv(8) AND 
	clkdiv(9));

FTCPE_clkdiv23: FTCPE port map (clkdiv(23),clkdiv_T(23),clk,Reset,'0');
clkdiv_T(23) <= (clkdiv(0) AND clkdiv(20) AND clkdiv(21) AND 
	clkdiv(22) AND clkdiv(10) AND clkdiv(11) AND clkdiv(12) AND 
	clkdiv(13) AND clkdiv(14) AND clkdiv(15) AND clkdiv(16) AND 
	clkdiv(17) AND clkdiv(18) AND clkdiv(19) AND clkdiv(1) AND clkdiv(2) AND 
	clkdiv(3) AND clkdiv(4) AND clkdiv(5) AND clkdiv(6) AND clkdiv(7) AND 
	clkdiv(8) AND clkdiv(9));

FTCPE_clkdiv24: FTCPE port map (clkdiv(24),clkdiv_T(24),clk,Reset,'0');
clkdiv_T(24) <= (clkdiv(0) AND clkdiv(20) AND clkdiv(21) AND 
	clkdiv(22) AND clkdiv(23) AND clkdiv(10) AND clkdiv(11) AND 
	clkdiv(12) AND clkdiv(13) AND clkdiv(14) AND clkdiv(15) AND 
	clkdiv(16) AND clkdiv(17) AND clkdiv(18) AND clkdiv(19) AND 
	clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND clkdiv(4) AND clkdiv(5) AND 
	clkdiv(6) AND clkdiv(7) AND clkdiv(8) AND clkdiv(9));

FTCPE_clkdiv2: FTCPE port map (clkdiv(2),clkdiv_T(2),clk,Reset,'0');
clkdiv_T(2) <= (clkdiv(0) AND clkdiv(1));

FTCPE_clkdiv3: FTCPE port map (clkdiv(3),clkdiv_T(3),clk,Reset,'0');
clkdiv_T(3) <= (clkdiv(0) AND clkdiv(1) AND clkdiv(2));

FTCPE_clkdiv4: FTCPE port map (clkdiv(4),clkdiv_T(4),clk,Reset,'0');
clkdiv_T(4) <= (clkdiv(0) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3));

FTCPE_clkdiv5: FTCPE port map (clkdiv(5),clkdiv_T(5),clk,Reset,'0');
clkdiv_T(5) <= (clkdiv(0) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND 
	clkdiv(4));

FTCPE_clkdiv6: FTCPE port map (clkdiv(6),clkdiv_T(6),clk,Reset,'0');
clkdiv_T(6) <= (clkdiv(0) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND 
	clkdiv(4) AND clkdiv(5));

FTCPE_clkdiv7: FTCPE port map (clkdiv(7),clkdiv_T(7),clk,Reset,'0');
clkdiv_T(7) <= (clkdiv(0) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND 
	clkdiv(4) AND clkdiv(5) AND clkdiv(6));

FTCPE_clkdiv8: FTCPE port map (clkdiv(8),clkdiv_T(8),clk,Reset,'0');
clkdiv_T(8) <= (clkdiv(0) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND 
	clkdiv(4) AND clkdiv(5) AND clkdiv(6) AND clkdiv(7));

FTCPE_clkdiv9: FTCPE port map (clkdiv(9),clkdiv_T(9),clk,Reset,'0');
clkdiv_T(9) <= (clkdiv(0) AND clkdiv(1) AND clkdiv(2) AND clkdiv(3) AND 
	clkdiv(4) AND clkdiv(5) AND clkdiv(6) AND clkdiv(7) AND clkdiv(8));

FTCPE_counter0: FTCPE port map (counter(0),counter_T(0),counter_C(0),Reset,'0');
counter_T(0) <= ((lcd_rs_OBUF.EXP)
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	NOT counter(6))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	NOT counter(4) AND NOT counter(5))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	NOT counter(3) AND NOT counter(0) AND NOT counter(1) AND NOT counter(2) AND 
	NOT counter(5)));
counter_C(0) <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND 
	clkdiv(23) AND clkdiv(24)));

FTCPE_counter1: FTCPE port map (counter(1),counter_T(1),counter_C(1),Reset,'0');
counter_T(1) <= ((state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	counter(0) AND NOT counter(6))
	OR (NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3 AND NOT flag AND 
	counter(1))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	counter(0) AND NOT counter(4) AND NOT counter(5)));
counter_C(1) <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND 
	clkdiv(23) AND clkdiv(24)));

FTCPE_counter2: FTCPE port map (counter(2),counter_T(2),counter_C(2),Reset,'0');
counter_T(2) <= ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3 AND NOT flag AND 
	counter(2))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	counter(0) AND counter(1) AND NOT counter(6))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	counter(0) AND NOT counter(4) AND counter(1) AND NOT counter(5)));
counter_C(2) <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND 
	clkdiv(23) AND clkdiv(24)));

FTCPE_counter3: FTCPE port map (counter(3),counter_T(3),counter_C(3),Reset,'0');
counter_T(3) <= ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3 AND 
	counter(3) AND NOT flag)
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	counter(0) AND counter(1) AND counter(2) AND NOT counter(6))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	counter(0) AND NOT counter(4) AND counter(1) AND counter(2) AND 
	NOT counter(5)));
counter_C(3) <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND 
	clkdiv(23) AND clkdiv(24)));

FTCPE_counter4: FTCPE port map (counter(4),counter_T(4),counter_C(4),Reset,'0');
counter_T(4) <= ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3 AND 
	counter(4) AND NOT flag)
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	counter(3) AND counter(0) AND counter(1) AND counter(2) AND 
	NOT counter(6))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	counter(3) AND counter(0) AND NOT counter(4) AND counter(1) AND 
	counter(2) AND NOT counter(5)));
counter_C(4) <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND 
	clkdiv(23) AND clkdiv(24)));

FTCPE_counter5: FTCPE port map (counter(5),counter_T(5),counter_C(5),Reset,'0');
counter_T(5) <= ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3 AND NOT flag AND 
	counter(5))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	counter(3) AND counter(0) AND counter(4) AND counter(1) AND 
	counter(2) AND NOT counter(6)));
counter_C(5) <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND 
	clkdiv(23) AND clkdiv(24)));

FTCPE_counter6: FTCPE port map (counter(6),counter_T(6),counter_C(6),Reset,'0');
counter_T(6) <= ((NOT state_FFT1 AND NOT state_FFT2 AND NOT state_FFT3 AND NOT flag AND 
	counter(6))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	counter(3) AND counter(0) AND counter(4) AND counter(1) AND 
	counter(2) AND counter(5) AND NOT counter(6)));
counter_C(6) <= NOT ((clkdiv(20) AND clkdiv(21) AND clkdiv(22) AND 
	clkdiv(23) AND clkdiv(24)));


data(1)_BUFR <= ((EXP26_.EXP)
	OR (EXP27_.EXP)
	OR (state_FFT1 AND state_FFT2 AND counter(0) AND 
	counter(4) AND counter(6))
	OR (state_FFT1 AND state_FFT2 AND counter(3) AND 
	NOT counter(0) AND NOT counter(4) AND NOT counter(1) AND counter(5))
	OR (state_FFT1 AND state_FFT2 AND counter(3) AND 
	NOT counter(4) AND NOT counter(1) AND counter(2) AND counter(5))
	OR (state_FFT1 AND state_FFT2 AND NOT counter(3) AND 
	counter(0) AND counter(4) AND counter(1) AND NOT counter(2))
	OR (state_FFT1 AND state_FFT2 AND counter(3) AND 
	counter(0) AND NOT counter(4) AND counter(1) AND NOT counter(2) AND 
	NOT counter(5) AND NOT counter(6)));


data(2)_BUFR <= NOT (((EXP25_.EXP)
	OR (state_FFT2 AND NOT state_FFT3 AND counter(0) AND 
	counter(4) AND counter(1) AND counter(2) AND NOT counter(5) AND 
	NOT counter(6))
	OR (state_FFT2 AND NOT state_FFT3 AND counter(0) AND 
	NOT counter(4) AND NOT counter(1) AND counter(2) AND NOT counter(5) AND 
	counter(6))));


data(4)_BUFR <= ((EXP21_.EXP)
	OR (EXP22_.EXP)
	OR (NOT state_FFT1 AND NOT state_FFT2)
	OR (NOT state_FFT2 AND NOT state_FFT3)
	OR (state_FFT1 AND NOT state_FFT3 AND counter(5) AND 
	counter(6))
	OR (state_FFT1 AND NOT state_FFT3 AND counter(0) AND 
	counter(4) AND counter(6))
	OR (state_FFT1 AND NOT state_FFT3 AND counter(4) AND 
	counter(2) AND counter(6)));


data(5)_BUFR <= ((EXP15_.EXP)
	OR (EXP16_.EXP)
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	NOT counter(1) AND counter(2) AND NOT counter(6))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	NOT counter(3) AND NOT counter(4) AND NOT counter(5) AND counter(6))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	counter(3) AND NOT counter(0) AND NOT counter(4) AND NOT counter(2) AND 
	NOT counter(5))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	counter(0) AND NOT counter(4) AND NOT counter(2) AND counter(5) AND 
	NOT counter(6))
	OR (state_FFT1 AND state_FFT2 AND NOT state_FFT3 AND 
	NOT counter(0) AND counter(4) AND counter(1) AND counter(5) AND 
	NOT counter(6)));


data(6)_BUFR <= NOT (((EXP18_.EXP)
	OR (EXP28_.EXP)
	OR (state_FFT1 AND NOT counter(3) AND NOT counter(4) AND 
	NOT counter(5) AND counter(6))
	OR (state_FFT1 AND counter(3) AND NOT counter(0) AND 
	NOT counter(4) AND NOT counter(1) AND NOT counter(2) AND NOT counter(5))
	OR (state_FFT1 AND counter(0) AND counter(4) AND 
	counter(1) AND counter(2) AND NOT counter(5) AND NOT counter(6))
	OR (state_FFT1 AND NOT counter(0) AND counter(4) AND 
	counter(1) AND NOT counter(2) AND counter(5) AND NOT counter(6))
	OR (state_FFT1 AND NOT counter(0) AND NOT counter(4) AND 
	counter(1) AND counter(2) AND counter(5) AND NOT counter(6))));