lcd.map.qmsg

这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 13 19:29:20 2005 " "Info: Processing started: Tue Dec 13 19:29:20 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd -c lcd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd -c lcd" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clklogic.gdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clklogic.gdf" { { "Info" "ISGN_ENTITY_NAME" "1 clklogic " "Info: Found entity 1: clklogic" {  } { { "clklogic.gdf" "" { Schematic "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/clklogic.gdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lcd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcd-Behavioral " "Info: Found design unit 1: lcd-Behavioral" {  } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 lcd " "Info: Found entity 1: lcd" {  } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "char_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file char_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 char_ram-fun " "Info: Found design unit 1: char_ram-fun" {  } { { "char_ram.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/char_ram.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 char_ram " "Info: Found entity 1: char_ram" {  } { { "char_ram.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/char_ram.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd " "Info: Elaborating entity \"lcd\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "char_ram char_ram:aa " "Info: Elaborating entity \"char_ram\" for hierarchy \"char_ram:aa\"" {  } { { "lcd.vhd" "aa" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 126 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "state\[10\] data_in GND " "Warning: Reduced register \"state\[10\]\" with stuck data_in port to stuck value GND" {  } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 56 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "state\[8\] data_in GND " "Warning: Reduced register \"state\[8\]\" with stuck data_in port to stuck value GND" {  } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 56 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "state\[6\] data_in GND " "Warning: Reduced register \"state\[6\]\" with stuck data_in port to stuck value GND" {  } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 56 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "state\[1\] data_in GND " "Warning: Reduced register \"state\[1\]\" with stuck data_in port to stuck value GND" {  } { { "lcd.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 56 -1 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "div_counter\[0\]~16 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"div_counter\[0\]~16\"" {  } { { "lcd.vhd" "div_counter\[0\]~16" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验1/lcd液晶显示/lcd/lcd.vhd" 58 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "39 " "Info: Ignored 39 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "39 " "Info: Ignored 39 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "Reset " "Info: Promoted clear signal driven by pin \"Reset\" to global clear signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "125 " "Info: Implemented 125 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "99 " "Info: Implemented 99 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "12 " "Info: Implemented 12 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 13 19:29:37 2005 " "Info: Processing ended: Tue Dec 13 19:29:37 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" {  } {  } 0}  } {  } 0}