add.hier_info

来自「这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一」· HIER_INFO 代码 · 共 26 行

|add
a[0] => add~0.IN3
a[1] => add~0.IN2
a[2] => add~0.IN1
b[0] => add~0.IN6
b[1] => add~0.IN5
b[2] => add~0.IN4
c[0] <= <VCC>
c[1] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
c[2] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
c[3] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
c[4] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
c[5] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
c[6] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
c[7] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
en[0] <= <GND>
en[1] <= <GND>
en[2] <= <GND>
en[3] <= <GND>
en[4] <= <GND>
en[5] <= <GND>
en[6] <= <GND>
en[7] <= <GND>