📄 24.rpt
字号:
- 3 - E 24 AND2 1 1 1 0 |COUNTER24:1|:258
- 6 - E 24 AND2 1 1 1 0 |COUNTER24:1|:264
- 5 - E 24 AND2 1 1 1 0 |COUNTER24:1|:270
- 8 - E 24 AND2 1 1 1 0 |COUNTER24:1|:276
- 2 - E 24 AND2 1 1 1 0 |COUNTER24:1|:282
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\ahdldigital\24.rpt
24
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
E: 2/ 96( 2%) 0/ 48( 0%) 9/ 48( 18%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\ahdldigital\24.rpt
24
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 cp
Device-Specific Information: f:\ahdldigital\24.rpt
24
** EQUATIONS **
clr : INPUT;
cp : INPUT;
ec : INPUT;
s : INPUT;
-- Node name is 'bin0'
-- Equation name is 'bin0', type is output
bin0 = _LC2_E24;
-- Node name is 'bin1'
-- Equation name is 'bin1', type is output
bin1 = _LC8_E24;
-- Node name is 'bin2'
-- Equation name is 'bin2', type is output
bin2 = _LC5_E24;
-- Node name is 'bin3'
-- Equation name is 'bin3', type is output
bin3 = _LC6_E24;
-- Node name is 'bin4'
-- Equation name is 'bin4', type is output
bin4 = _LC3_E24;
-- Node name is 'cy24'
-- Equation name is 'cy24', type is output
cy24 = _LC4_E22;
-- Node name is '|COUNTER24:1|LPM_ADD_SUB:78|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_E24', type is buried
_LC4_E24 = LCELL( _EQ001);
_EQ001 = _LC1_E22 & _LC3_E22;
-- Node name is '|COUNTER24:1|LPM_ADD_SUB:78|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_E22', type is buried
_LC6_E22 = LCELL( _EQ002);
_EQ002 = _LC4_E24 & _LC8_E22;
-- Node name is '|COUNTER24:1|LPM_ADD_SUB:78|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_E22', type is buried
_LC7_E22 = LCELL( _EQ003);
_EQ003 = _LC2_E22 & _LC4_E24 & _LC8_E22;
-- Node name is '|COUNTER24:1|:17' = '|COUNTER24:1|q0'
-- Equation name is '_LC3_E22', type is buried
_LC3_E22 = DFFE( _EQ004, cp, VCC, VCC, VCC);
_EQ004 = !ec & !_LC1_E24 & _LC3_E22
# ec & !_LC1_E24 & !_LC3_E22;
-- Node name is '|COUNTER24:1|:16' = '|COUNTER24:1|q1'
-- Equation name is '_LC1_E22', type is buried
_LC1_E22 = DFFE( _EQ005, cp, VCC, VCC, VCC);
_EQ005 = _LC1_E22 & !_LC1_E24 & !_LC3_E22
# ec & !_LC1_E22 & !_LC1_E24 & _LC3_E22
# !ec & _LC1_E22 & !_LC1_E24;
-- Node name is '|COUNTER24:1|:15' = '|COUNTER24:1|q2'
-- Equation name is '_LC8_E22', type is buried
_LC8_E22 = DFFE( _EQ006, cp, VCC, VCC, VCC);
_EQ006 = !_LC1_E24 & !_LC4_E24 & _LC8_E22
# ec & !_LC1_E24 & _LC4_E24 & !_LC8_E22
# !ec & !_LC1_E24 & _LC8_E22;
-- Node name is '|COUNTER24:1|:14' = '|COUNTER24:1|q3'
-- Equation name is '_LC2_E22', type is buried
_LC2_E22 = DFFE( _EQ007, cp, VCC, VCC, VCC);
_EQ007 = !_LC1_E24 & _LC2_E22 & !_LC6_E22
# ec & !_LC1_E24 & !_LC2_E22 & _LC6_E22
# !ec & !_LC1_E24 & _LC2_E22;
-- Node name is '|COUNTER24:1|:13' = '|COUNTER24:1|q4'
-- Equation name is '_LC5_E22', type is buried
_LC5_E22 = DFFE( _EQ008, cp, VCC, VCC, VCC);
_EQ008 = !_LC1_E24 & _LC5_E22 & !_LC7_E22
# ec & !_LC1_E24 & !_LC5_E22 & _LC7_E22
# !ec & !_LC1_E24 & _LC5_E22;
-- Node name is '|COUNTER24:1|~51~1'
-- Equation name is '_LC7_E24', type is buried
-- synthesized logic cell
_LC7_E24 = LCELL( _EQ009);
_EQ009 = _LC2_E22 & _LC3_E22
# _LC3_E22 & !_LC8_E22
# !_LC1_E22 & _LC3_E22
# _LC1_E22 & _LC2_E22
# _LC1_E22 & !_LC8_E22
# _LC1_E22 & !_LC3_E22
# !_LC2_E22 & !_LC8_E22
# !_LC1_E22 & !_LC2_E22
# !_LC2_E22 & !_LC3_E22
# _LC2_E22 & _LC8_E22
# !_LC1_E22 & _LC8_E22
# !_LC3_E22 & _LC8_E22;
-- Node name is '|COUNTER24:1|:51'
-- Equation name is '_LC1_E24', type is buried
!_LC1_E24 = _LC1_E24~NOT;
_LC1_E24~NOT = LCELL( _EQ010);
_EQ010 = !clr & !_LC5_E22
# !clr & _LC7_E24;
-- Node name is '|COUNTER24:1|:195'
-- Equation name is '_LC4_E22', type is buried
_LC4_E22 = LCELL( _EQ011);
_EQ011 = !_LC2_E22 & _LC4_E24 & _LC5_E22 & _LC8_E22;
-- Node name is '|COUNTER24:1|:258'
-- Equation name is '_LC3_E24', type is buried
_LC3_E24 = LCELL( _EQ012);
_EQ012 = _LC5_E22 & s;
-- Node name is '|COUNTER24:1|:264'
-- Equation name is '_LC6_E24', type is buried
_LC6_E24 = LCELL( _EQ013);
_EQ013 = _LC2_E22 & s;
-- Node name is '|COUNTER24:1|:270'
-- Equation name is '_LC5_E24', type is buried
_LC5_E24 = LCELL( _EQ014);
_EQ014 = _LC8_E22 & s;
-- Node name is '|COUNTER24:1|:276'
-- Equation name is '_LC8_E24', type is buried
_LC8_E24 = LCELL( _EQ015);
_EQ015 = _LC1_E22 & s;
-- Node name is '|COUNTER24:1|:282'
-- Equation name is '_LC2_E24', type is buried
_LC2_E24 = LCELL( _EQ016);
_EQ016 = _LC3_E22 & s;
Project Information f:\ahdldigital\24.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,851K
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