📄 60.rpt
字号:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\ahdldigital\60.rpt
60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 cp
Device-Specific Information: f:\ahdldigital\60.rpt
60
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 7 |COUNTER60:1|:180
Device-Specific Information: f:\ahdldigital\60.rpt
60
** EQUATIONS **
clr : INPUT;
cp : INPUT;
ec : INPUT;
s : INPUT;
-- Node name is 'bin0'
-- Equation name is 'bin0', type is output
bin0 = _LC2_A4;
-- Node name is 'bin1'
-- Equation name is 'bin1', type is output
bin1 = _LC6_A6;
-- Node name is 'bin2'
-- Equation name is 'bin2', type is output
bin2 = _LC4_A10;
-- Node name is 'bin3'
-- Equation name is 'bin3', type is output
bin3 = _LC8_A10;
-- Node name is 'bin4'
-- Equation name is 'bin4', type is output
bin4 = _LC5_A6;
-- Node name is 'bin5'
-- Equation name is 'bin5', type is output
bin5 = _LC1_A6;
-- Node name is 'cy60'
-- Equation name is 'cy60', type is output
cy60 = _LC2_A6;
-- Node name is '|COUNTER60:1|:19' = '|COUNTER60:1|dly'
-- Equation name is '_LC8_A6', type is buried
_LC8_A6 = DFFE( _LC7_A6, GLOBAL( cp), VCC, VCC, !_LC3_A6);
-- Node name is '|COUNTER60:1|LPM_ADD_SUB:83|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A4', type is buried
_LC7_A4 = LCELL( _EQ001);
_EQ001 = _LC3_A4 & _LC5_A4 & _LC6_A4;
-- Node name is '|COUNTER60:1|LPM_ADD_SUB:83|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = LCELL( _EQ002);
_EQ002 = _LC3_A4 & _LC4_A4 & _LC5_A4 & _LC6_A4;
-- Node name is '|COUNTER60:1|:18' = '|COUNTER60:1|q0'
-- Equation name is '_LC6_A4', type is buried
_LC6_A4 = DFFE( _EQ003, GLOBAL( cp), !_LC3_A6, VCC, VCC);
_EQ003 = !ec & _LC6_A4
# ec & !_LC6_A4;
-- Node name is '|COUNTER60:1|:17' = '|COUNTER60:1|q1'
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = DFFE( _EQ004, GLOBAL( cp), !_LC3_A6, VCC, VCC);
_EQ004 = _LC3_A4 & !_LC6_A4
# ec & !_LC3_A4 & _LC6_A4
# !ec & _LC3_A4;
-- Node name is '|COUNTER60:1|:16' = '|COUNTER60:1|q2'
-- Equation name is '_LC5_A4', type is buried
_LC5_A4 = DFFE( _EQ005, GLOBAL( cp), !_LC3_A6, VCC, VCC);
_EQ005 = !_LC3_A4 & _LC5_A4
# _LC5_A4 & !_LC6_A4
# ec & _LC3_A4 & !_LC5_A4 & _LC6_A4
# !ec & _LC5_A4;
-- Node name is '|COUNTER60:1|:15' = '|COUNTER60:1|q3'
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = DFFE( _EQ006, GLOBAL( cp), !_LC3_A6, VCC, VCC);
_EQ006 = _LC4_A4 & !_LC7_A4
# ec & !_LC4_A4 & _LC7_A4
# !ec & _LC4_A4;
-- Node name is '|COUNTER60:1|:14' = '|COUNTER60:1|q4'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = DFFE( _EQ007, GLOBAL( cp), !_LC3_A6, VCC, VCC);
_EQ007 = !_LC1_A4 & _LC4_A6
# ec & _LC1_A4 & !_LC4_A6
# !ec & _LC4_A6;
-- Node name is '|COUNTER60:1|:13' = '|COUNTER60:1|q5'
-- Equation name is '_LC7_A6', type is buried
_LC7_A6 = DFFE( _EQ008, GLOBAL( cp), !_LC3_A6, VCC, VCC);
_EQ008 = !_LC4_A6 & _LC7_A6
# !_LC1_A4 & _LC7_A6
# ec & _LC1_A4 & _LC4_A6 & !_LC7_A6
# !ec & _LC7_A6;
-- Node name is '|COUNTER60:1|:169'
-- Equation name is '_LC2_A6', type is buried
_LC2_A6 = LCELL( _EQ009);
_EQ009 = !_LC7_A6 & _LC8_A6;
-- Node name is '|COUNTER60:1|~173~1'
-- Equation name is '_LC8_A4', type is buried
-- synthesized logic cell
_LC8_A4 = LCELL( _EQ010);
_EQ010 = !_LC4_A4
# !_LC5_A4
# _LC3_A4
# _LC6_A4;
-- Node name is '|COUNTER60:1|:180'
-- Equation name is '_LC3_A6', type is buried
!_LC3_A6 = _LC3_A6~NOT;
_LC3_A6~NOT = LCELL( _EQ011);
_EQ011 = !clr & _LC8_A4
# !clr & !_LC7_A6
# !clr & !_LC4_A6;
-- Node name is '|COUNTER60:1|:204'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = LCELL( _EQ012);
_EQ012 = _LC7_A6 & s;
-- Node name is '|COUNTER60:1|:210'
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = LCELL( _EQ013);
_EQ013 = _LC4_A6 & s;
-- Node name is '|COUNTER60:1|:216'
-- Equation name is '_LC8_A10', type is buried
_LC8_A10 = LCELL( _EQ014);
_EQ014 = _LC4_A4 & s;
-- Node name is '|COUNTER60:1|:222'
-- Equation name is '_LC4_A10', type is buried
_LC4_A10 = LCELL( _EQ015);
_EQ015 = _LC5_A4 & s;
-- Node name is '|COUNTER60:1|:228'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = LCELL( _EQ016);
_EQ016 = _LC3_A4 & s;
-- Node name is '|COUNTER60:1|:234'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = LCELL( _EQ017);
_EQ017 = _LC6_A4 & s;
Project Information f:\ahdldigital\60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,243K
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