📄 timer_set.rpt
字号:
- 6 - A 19 AND2 s ! 0 3 0 4 ~1713~1
- 8 - A 19 AND2 s ! 0 3 0 13 ~1713~2
- 7 - A 15 AND2 s ! 0 3 0 13 ~1720~1
- 7 - A 18 AND2 s ! 0 3 0 2 ~1727~1
- 1 - A 15 AND2 s 0 3 0 9 ~1741~1
- 1 - A 24 AND2 s 0 3 0 9 ~1748~1
- 3 - A 15 OR2 s 0 4 0 9 ~1769~1
- 2 - A 15 OR2 s 0 4 0 9 ~1776~1
- 8 - A 15 AND2 s ! 0 2 0 11 ~1797~1
- 8 - A 06 OR2 ! 0 4 0 2 :1811
- 5 - A 06 OR2 ! 0 4 0 2 :1818
- 1 - A 07 OR2 s 0 3 0 5 ~1825~1
- 4 - A 06 AND2 0 2 0 1 :1825
- 6 - A 06 OR2 ! 0 2 0 1 :1832
- 1 - A 14 AND2 0 4 0 2 :1839
- 2 - A 07 AND2 0 4 0 2 :1846
- 5 - A 15 AND2 s ! 0 4 0 4 ~1853~1
- 3 - A 24 AND2 s ! 0 4 0 4 ~1860~1
- 4 - A 15 AND2 s 0 4 0 4 ~1881~1
- 6 - A 14 OR2 s 0 3 0 5 ~1909~1
- 5 - A 13 OR2 ! 0 4 0 2 :1923
- 4 - A 13 OR2 ! 0 4 0 2 :1930
- 2 - A 13 AND2 0 2 0 1 :1937
- 1 - A 18 OR2 ! 0 2 0 1 :1944
- 5 - A 18 OR2 ! 0 4 0 2 :1951
- 4 - A 18 OR2 ! 0 4 0 2 :1958
- 4 - A 21 AND2 s ! 0 2 0 6 ~2000~1
- 7 - A 14 AND2 s 0 3 0 6 ~2021~1
- 5 - A 14 OR2 s 0 3 0 7 ~2035~1
- 7 - A 19 AND2 s ! 0 2 0 12 ~2042~1
- 6 - A 15 AND2 s ! 0 2 0 6 ~2077~1
- 4 - A 19 AND2 s ! 0 2 0 7 ~2084~1
- 5 - A 17 OR2 s 0 2 0 1 ~2084~2
- 6 - A 17 OR2 s ! 0 2 0 1 ~2091~1
- 2 - A 21 OR2 s ! 0 3 0 2 ~2531~1
- 6 - A 08 AND2 ! 0 4 0 2 :2774
- 2 - A 20 AND2 ! 0 2 0 2 :2867
- 7 - A 21 OR2 s 0 3 0 1 ~2902~1
- 1 - A 13 AND2 s 0 2 0 2 ~2927~1
- 5 - A 08 OR2 ! 0 4 0 1 :2927
- 1 - A 03 OR2 s 0 2 0 2 ~2962~1
- 7 - A 16 OR2 s 0 3 0 1 ~2962~2
- 4 - A 08 OR2 ! 0 3 0 1 :2962
- 8 - A 07 OR2 s 0 4 0 3 ~2987~1
- 2 - A 12 AND2 s 0 2 0 1 ~2987~2
- 4 - A 17 OR2 ! 0 4 0 2 :3026
- 3 - A 17 OR2 s 0 3 0 3 ~3055~1
- 4 - A 20 AND2 s 0 3 0 2 ~3055~2
- 3 - A 20 OR2 0 3 0 1 :3056
- 5 - A 07 OR2 s ! 0 4 0 2 ~3085~1
- 6 - A 07 OR2 s ! 0 4 0 3 ~3085~2
- 6 - A 21 OR2 s ! 0 4 0 2 ~3085~3
- 8 - A 08 OR2 0 4 0 1 :3086
- 4 - A 14 OR2 s 0 3 0 2 ~3115~1
- 5 - A 16 AND2 s 0 2 0 2 ~3115~2
- 1 - A 16 AND2 s 0 3 0 3 ~3115~3
- 6 - A 16 OR2 s ! 0 3 0 2 ~3145~1
- 3 - A 16 OR2 s ! 0 4 0 2 ~3145~2
- 8 - A 01 OR2 s ! 0 2 0 3 ~3145~3
- 3 - A 08 OR2 0 4 0 1 :3145
- 2 - A 01 OR2 s 0 3 0 3 ~3175~1
- 4 - A 01 AND2 s 0 4 0 3 ~3175~2
- 8 - A 12 OR2 0 4 0 1 :3176
- 1 - A 20 OR2 ! 0 4 0 2 :3221
- 7 - A 20 OR2 ! 0 4 0 1 :3244
- 1 - A 21 OR2 s ! 0 4 0 3 ~3274~1
- 5 - A 21 OR2 s ! 0 4 0 2 ~3274~2
- 8 - A 21 OR2 ! 0 4 0 1 :3274
- 3 - A 14 OR2 s 0 3 0 3 ~3304~1
- 4 - B 23 OR2 s ! 0 3 0 2 ~3304~2
- 2 - A 16 OR2 ! 0 4 0 1 :3304
- 7 - A 03 OR2 s ! 0 2 0 2 ~3334~1
- 3 - A 01 OR2 ! 0 4 0 1 :3334
- 3 - A 07 OR2 s 0 4 0 3 ~3364~1
- 6 - A 01 OR2 s ! 0 3 0 1 ~3364~2
- 1 - A 01 OR2 ! 0 4 0 9 :3364
- 1 - A 17 OR2 ! 0 4 0 2 :3398
- 5 - A 20 OR2 s 0 3 0 1 ~3409~1
- 8 - A 20 OR2 ! 0 3 0 1 :3410
- 2 - A 14 OR2 s ! 0 3 0 3 ~3427~1
- 8 - A 14 OR2 s 0 3 0 4 ~3427~2
- 6 - A 20 OR2 ! 0 4 0 1 :3428
- 3 - A 18 AND2 s ! 0 2 0 4 ~3457~1
- 3 - A 21 OR2 ! 0 4 0 1 :3457
- 8 - A 16 OR2 ! 0 4 0 1 :3470
- 8 - B 23 OR2 s ! 0 2 0 1 ~3487~1
- 6 - B 23 AND2 s 0 2 0 4 ~3487~2
- 4 - A 16 OR2 ! 0 4 0 1 :3499
- 2 - A 06 AND2 s ! 0 2 0 5 ~3517~1
- 8 - A 03 OR2 s 0 3 0 2 ~3517~2
- 6 - A 03 OR2 ! 0 4 0 1 :3517
- 7 - A 01 OR2 ! 0 3 0 5 :3529
- 4 - A 24 OR2 s ! 0 4 0 3 ~3547~1
- 2 - A 24 OR2 s 0 4 0 4 ~3547~2
- 5 - A 01 OR2 ! 0 4 0 5 :3547
- 7 - A 09 OR2 ! 0 4 0 1 :3560
- 7 - A 17 OR2 ! 0 4 0 1 :3586
- 8 - A 17 OR2 ! 0 4 0 1 :3592
- 2 - A 17 OR2 ! 0 4 0 1 :3598
- 1 - A 23 OR2 ! 0 4 0 1 :3604
- 4 - A 23 OR2 ! 0 4 0 1 :3608
- 3 - A 23 OR2 ! 0 4 0 1 :3610
- 5 - A 23 OR2 ! 0 4 0 1 :3616
- 7 - A 23 OR2 ! 0 4 0 1 :3620
- 6 - A 23 OR2 ! 0 4 0 1 :3622
- 8 - A 23 OR2 ! 0 4 0 1 :3628
- 2 - A 23 OR2 ! 0 4 0 1 :3634
- 6 - A 18 OR2 ! 0 4 0 1 :3638
- 6 - A 13 OR2 ! 0 4 0 1 :3652
- 7 - A 13 OR2 ! 0 4 0 1 :3658
- 8 - A 13 OR2 ! 0 3 0 1 :3670
- 3 - A 13 OR2 ! 0 3 0 1 :3682
- 7 - A 06 OR2 ! 0 4 0 1 :3686
- 3 - A 06 OR2 ! 0 4 0 7 :3700
- 2 - A 22 OR2 ! 0 4 0 1 :3704
- 1 - A 06 OR2 ! 0 4 0 1 :3706
- 4 - A 22 OR2 ! 0 4 0 1 :3710
- 3 - A 22 OR2 ! 0 4 0 1 :3712
- 6 - A 22 OR2 ! 0 4 0 1 :3716
- 5 - A 22 OR2 ! 0 4 0 1 :3718
- 8 - A 22 OR2 ! 0 4 0 1 :3722
- 7 - A 22 OR2 ! 0 4 0 1 :3724
- 1 - A 22 OR2 ! 0 4 0 4 :3730
- 8 - C 03 OR2 0 3 0 5 :3770
- 8 - A 18 OR2 s ! 0 3 0 4 ~3797~1
- 8 - A 09 OR2 s ! 0 4 0 2 ~3797~2
- 7 - A 12 OR2 s ! 0 2 0 1 ~3797~3
- 6 - A 12 AND2 0 4 1 17 :3797
- 2 - A 18 OR2 s 0 3 0 4 ~3802~1
- 2 - A 19 OR2 s 0 4 0 2 ~3802~2
- 1 - A 08 OR2 ! 0 4 1 9 :3802
- 6 - A 09 OR2 s ! 0 4 0 1 ~3803~1
- 1 - A 12 OR2 s 0 4 0 2 ~3804~1
- 7 - A 08 OR2 s ! 0 4 0 1 ~3804~2
- 4 - A 09 OR2 ! 0 4 1 9 :3808
- 2 - A 08 OR2 s ! 0 3 0 1 ~3810~1
- 2 - B 19 OR2 s 0 3 0 2 ~3814~1
- 2 - B 13 OR2 s 0 2 0 2 ~3814~2
- 3 - B 13 OR2 s 0 3 0 1 ~3814~3
- 6 - B 19 OR2 s 0 3 0 2 ~3814~4
- 1 - B 19 OR2 s 0 4 0 1 ~3814~5
- 4 - B 13 OR2 s 0 4 0 1 ~3814~6
- 7 - B 13 OR2 s 0 4 0 1 ~3814~7
- 5 - B 13 OR2 s 0 4 0 1 ~3814~8
- 5 - B 20 OR2 s 0 3 0 2 ~3814~9
- 6 - B 20 OR2 s 0 4 0 1 ~3814~10
- 7 - B 20 OR2 s 0 4 0 1 ~3814~11
- 8 - B 20 OR2 s 0 3 0 1 ~3814~12
- 8 - B 19 OR2 s 0 4 0 1 ~3814~13
- 3 - B 19 OR2 s 0 4 0 1 ~3814~14
- 4 - B 20 OR2 s 0 4 0 1 ~3814~15
- 4 - A 12 OR2 ! 0 4 1 9 :3814
- 3 - B 20 AND2 s 0 4 0 1 ~3816~1
- 8 - B 13 OR2 s ! 0 3 0 3 ~3816~2
- 7 - B 19 AND2 s 0 4 0 1 ~3816~3
- 1 - A 19 OR2 s 0 3 0 4 ~3816~4
- 3 - A 12 OR2 s 0 2 0 2 ~3816~5
- 5 - A 12 OR2 s ! 0 4 0 1 ~3816~6
- 4 - A 02 AND2 0 4 0 6 :3833
- 6 - A 02 OR2 ! 0 4 0 6 :3838
- 5 - A 02 AND2 0 4 0 4 :3843
- 3 - A 02 AND2 0 4 0 2 :3848
- 7 - A 02 OR2 ! 0 4 0 5 :3853
- 2 - A 02 AND2 0 4 0 1 :3863
- 3 - A 04 AND2 0 4 0 5 :3868
- 2 - A 09 AND2 0 4 0 4 :3873
- 1 - A 09 AND2 0 4 0 4 :3878
- 3 - A 09 AND2 0 4 0 4 :3883
- 5 - A 09 OR2 ! 0 4 0 4 :3888
- 4 - A 03 AND2 0 4 0 3 :3893
- 5 - A 03 OR2 ! 0 4 0 5 :3898
- 2 - A 03 AND2 0 4 0 3 :3903
- 3 - A 03 AND2 0 4 0 3 :3908
- 1 - A 05 OR2 0 4 0 1 :3948
- 3 - A 10 OR2 s 0 3 0 2 ~4000~1
- 4 - A 04 OR2 s 0 4 0 1 ~4000~2
- 7 - A 04 OR2 s 0 2 0 1 ~4039~1
- 1 - A 04 OR2 s 0 4 0 2 ~4039~2
- 3 - A 05 OR2 0 4 0 1 :4051
- 7 - A 11 AND2 s 0 2 0 1 ~4065~1
- 8 - A 04 OR2 0 3 0 1 :4084
- 2 - A 04 OR2 0 4 0 1 :4098
- 4 - C 07 OR2 0 4 0 1 :4108
- 1 - A 02 OR2 s 0 4 0 1 ~4110~1
- 2 - A 05 OR2 0 4 0 2 :4132
- 6 - A 04 OR2 0 4 0 1 :4149
- 6 - A 11 OR2 0 4 0 1 :4159
- 8 - A 05 OR2 s 0 2 0 1 ~4207~1
- 4 - A 10 OR2 0 4 0 1 :4207
- 5 - A 04 OR2 s 0 4 0 3 ~4246~1
- 7 - A 05 OR2 0 2 0 1 :4246
- 4 - A 05 OR2 s 0 4 0 1 ~4267~1
- 6 - A 05 OR2 0 4 0 2 :4282
- 8 - A 02 OR2 s 0 4 0 5 ~4303~1
- 5 - A 05 OR2 s 0 3 0 1 ~4303~2
- 2 - A 10 OR2 s 0 2 0 4 ~4312~1
- 4 - A 11 OR2 0 4 0 1 :4312
- 1 - B 04 OR2 ! 0 2 0 1 :4321
- 3 - B 15 OR2 ! 0 3 0 3 :4328
- 6 - B 15 OR2 ! 1 2 0 3 :4346
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\max+plusii learning\course and others\vhdl\timer_set.rpt
timer_set
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 65/ 96( 67%) 35/ 48( 72%) 23/ 48( 47%) 0/16( 0%) 11/16( 68%) 0/16( 0%)
B: 14/ 96( 14%) 2/ 48( 4%) 30/ 48( 62%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 2/ 96( 2%) 13/ 48( 27%) 0/ 48( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
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