📄 decoder.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decoder IS
port(
INPUT: in STD_LOGIC_VECTOR( 3 DOWNTO 0);
output : out STD_LOGIC_VECTOR( 6 DOWNTO 0)
);
END decoder;
ARCHITECTURE decoder_arch OF decoder IS
begin
process(INPUT)
BEGIN
if( INPUT = "0000") then
output <= "1111110";
elsif( INPUT = "0001") then
output <="0110000";
elsif(INPUT = "0010") then
output <="1101101";
elsif( INPUT = "0011") then
output <="1111001";
elsif( INPUT = "0100") then
output <="0110011";
elsif(INPUT = "0101") then
output <="1011011";
elsif(INPUT = "0110") then
output <="0011111";
elsif(INPUT = "0111") then
output <="1110000";
elsif(INPUT = "1000") then
output <="1111111";
elsif(INPUT = "1001") then
output <="1110011";
END IF;
end process;
END decoder_arch;
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