📄 counter.rpt
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- 5 - C 20 OR2 s 0 4 0 3 ~1373~1
- 3 - C 21 AND2 s ! 0 4 0 4 ~1425~1
- 8 - C 21 OR2 ! 0 3 0 2 :1451
- 4 - C 21 OR2 s 0 4 0 6 ~1503~1
- 4 - C 20 OR2 s 0 4 0 3 ~1529~1
- 4 - C 09 AND2 s ! 0 4 0 4 ~1620~1
- 3 - C 06 OR2 s 0 4 0 3 ~1659~1
- 8 - C 06 AND2 0 3 0 1 :1672
- 7 - C 23 OR2 s 0 2 0 1 ~1711~1
- 4 - C 06 OR2 s 0 4 0 5 ~1724~1
- 1 - C 02 OR2 s 0 4 0 4 ~1737~1
- 6 - C 10 OR2 s 0 4 0 2 ~3247~1
- 6 - C 05 OR2 s 0 2 0 1 ~3247~2
- 7 - C 21 OR2 s 0 4 0 3 ~3247~3
- 3 - C 15 OR2 s ! 0 4 0 2 ~3247~4
- 6 - C 18 AND2 s 0 3 0 1 ~3247~5
- 8 - C 18 AND2 s 0 3 0 1 ~3247~6
- 2 - C 18 AND2 s 0 4 0 3 ~3247~7
- 5 - C 19 OR2 s ! 0 2 0 3 ~3275~1
- 6 - C 23 AND2 s 0 2 0 2 ~3275~2
- 4 - C 19 OR2 s 0 3 0 2 ~3275~3
- 8 - C 19 AND2 s ! 0 2 0 2 ~3275~4
- 6 - C 19 OR2 s ! 0 3 0 4 ~3275~5
- 7 - C 14 OR2 0 4 0 1 :3275
- 8 - C 09 AND2 s 0 2 0 1 ~3325~1
- 3 - C 09 AND2 s 0 4 0 2 ~3325~2
- 6 - C 08 OR2 s 0 3 0 3 ~3338~1
- 5 - C 08 AND2 s ! 0 3 0 3 ~3338~2
- 5 - C 18 OR2 0 3 0 1 :3338
- 3 - C 16 AND2 s ! 0 2 0 1 ~3382~1
- 8 - C 20 AND2 s ! 0 1 0 3 ~3382~2
- 1 - C 21 AND2 s 0 3 0 1 ~3382~3
- 4 - C 18 AND2 s 0 4 0 2 ~3382~4
- 8 - C 15 AND2 s 0 2 0 3 ~3407~1
- 2 - C 15 OR2 s 0 2 0 2 ~3407~2
- 6 - C 15 OR2 s 0 3 0 2 ~3407~3
- 1 - C 18 OR2 0 4 0 1 :3407
- 4 - C 14 OR2 0 4 0 1 :3445
- 2 - C 09 OR2 s ! 0 3 0 3 ~3485~1
- 1 - C 09 OR2 0 4 0 1 :3485
- 6 - C 21 OR2 s 0 4 0 3 ~3541~1
- 7 - C 03 OR2 s ! 0 4 0 5 ~3542~1
- 3 - C 18 OR2 0 4 0 1 :3542
- 2 - C 23 OR2 s ! 0 2 0 3 ~3572~1
- 5 - C 15 OR2 0 4 0 1 :3572
- 7 - C 06 OR2 s 0 4 0 4 ~3644~1
- 6 - C 06 OR2 s ! 0 3 0 4 ~3644~2
- 6 - C 09 OR2 0 4 0 1 :3644
- 5 - C 09 OR2 s 0 4 0 2 ~3667~1
- 7 - C 08 AND2 s 0 2 0 2 ~3667~2
- 2 - C 08 OR2 0 4 0 1 :3668
- 7 - C 18 AND2 s 0 3 0 1 ~3724~1
- 5 - C 21 OR2 0 4 0 1 :3724
- 1 - C 23 OR2 s 0 4 0 3 ~3731~1
- 4 - C 15 OR2 s ! 0 2 0 3 ~3731~2
- 5 - C 23 OR2 s 0 4 0 2 ~3754~1
- 2 - C 21 OR2 0 4 0 1 :3754
- 2 - C 16 AND2 s 0 2 0 1 ~3761~1
- 7 - C 19 OR2 s ! 0 4 0 2 ~3761~2
- 3 - C 05 OR2 0 3 0 1 :3787
- 5 - C 05 OR2 0 4 0 1 :3796
- 7 - C 09 OR2 0 4 0 1 :3809
- 4 - C 08 OR2 s 0 4 0 1 ~3844~1
- 8 - C 08 OR2 0 4 0 1 :3844
- 4 - C 16 OR2 0 4 0 1 :3854
- 5 - C 16 OR2 0 3 0 1 :3866
- 6 - C 16 OR2 s 0 2 0 2 ~3883~1
- 1 - C 16 AND2 0 3 0 1 :3883
- 1 - C 15 OR2 0 4 0 1 :3896
- 8 - C 16 OR2 0 4 0 1 :3925
- 1 - C 05 OR2 0 4 0 1 :3947
- 5 - C 06 OR2 0 4 0 1 :3962
- 2 - C 05 OR2 0 4 0 1 :3964
- 1 - C 06 OR2 0 4 0 1 :3976
- 3 - C 12 OR2 0 3 0 1 :3986
- 2 - C 12 OR2 0 3 0 1 :3988
- 4 - C 12 OR2 0 4 0 1 :4000
- 5 - C 12 OR2 0 4 0 1 :4004
- 6 - C 12 AND2 0 2 0 1 :4015
- 7 - C 12 OR2 0 4 0 1 :4019
- 8 - C 12 OR2 0 3 0 1 :4031
- 1 - C 12 AND2 0 2 0 1 :4039
- 1 - C 17 OR2 0 4 0 1 :4043
- 2 - C 17 OR2 0 3 0 1 :4055
- 3 - C 17 OR2 0 4 0 1 :4063
- 4 - C 17 OR2 0 4 0 1 :4067
- 5 - C 17 OR2 0 3 0 1 :4079
- 6 - C 17 OR2 0 3 0 1 :4087
- 8 - C 17 OR2 0 4 0 1 :4091
- 1 - C 14 OR2 ! 1 1 0 8 :4121
- 6 - C 24 OR2 ! 1 1 0 7 :4137
- 4 - C 01 OR2 s ! 0 2 0 7 ~4144~1
- 1 - C 08 OR2 ! 0 2 0 11 :4144
- 1 - C 11 OR2 ! 1 2 0 6 :4166
- 7 - C 11 OR2 ! 1 2 0 6 :4182
- 8 - C 05 OR2 ! 1 3 0 15 :4198
- 2 - C 10 OR2 s 1 3 0 1 ~4332~1
- 3 - C 10 OR2 s 0 4 0 1 ~4332~2
- 4 - C 11 AND2 s 0 2 0 5 ~4374~1
- 3 - C 13 AND2 s 0 2 0 1 ~4374~2
- 2 - C 24 AND2 s 0 2 0 4 ~4395~1
- 2 - C 13 OR2 1 3 0 1 :4399
- 5 - C 13 OR2 1 3 0 1 :4429
- 2 - C 06 OR2 s ! 0 3 0 2 ~4458~1
- 7 - C 05 OR2 s 0 3 0 1 ~4458~2
- 4 - C 05 AND2 s 0 3 0 3 ~4458~3
- 3 - C 14 AND2 s 0 2 0 4 ~4479~1
- 3 - C 08 OR2 s 0 4 0 3 ~4479~2
- 2 - C 22 AND2 s 0 4 0 2 ~4479~3
- 8 - C 14 OR2 0 4 0 1 :4483
- 8 - C 11 AND2 s 0 2 0 5 ~4494~1
- 6 - C 14 OR2 0 4 0 1 :4510
- 1 - C 24 OR2 0 4 0 1 :4531
- 5 - C 10 AND2 s 0 2 0 1 ~4557~1
- 7 - C 13 OR2 0 2 0 1 :4567
- 4 - C 10 AND2 s ! 0 2 0 4 ~4603~1
- 3 - C 07 AND2 s 0 2 0 2 ~4626~1
- 6 - C 07 AND2 s 0 2 0 1 ~4638~1
- 7 - C 24 OR2 1 1 1 0 :4856
- 1 - C 10 AND2 1 1 1 0 :4864
- 4 - C 13 AND2 1 1 1 0 :4870
- 3 - C 11 OR2 1 1 1 0 :4874
- 1 - C 07 AND2 1 1 1 0 :4882
- 5 - C 07 AND2 1 1 1 0 :4888
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\maxplus programme\numberlogic\lessondesign4\lessondesign\counter.rpt
counter
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 38/ 96( 39%) 29/ 48( 60%) 37/ 48( 77%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\maxplus programme\numberlogic\lessondesign4\lessondesign\counter.rpt
counter
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 CLK
Device-Specific Information:e:\maxplus programme\numberlogic\lessondesign4\lessondesign\counter.rpt
counter
** EQUATIONS **
CLK : INPUT;
emergency : INPUT;
-- Node name is ':22' = 'count0'
-- Equation name is 'count0', location is LC6_C13, type is buried.
count0 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = _LC5_C13 & !_LC6_C24
# _LC1_C14;
-- Node name is ':21' = 'count1'
-- Equation name is 'count1', location is LC1_C13, type is buried.
count1 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = !_LC1_C14 & _LC2_C13 & _LC8_C11
# !_LC1_C14 & _LC6_C24;
-- Node name is ':20' = 'count2'
-- Equation name is 'count2', location is LC2_C11, type is buried.
count2 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = !_LC4_C10 & _LC5_C11 & !_LC8_C5
# !_LC4_C10 & !_LC4_C11;
-- Node name is ':19' = 'count3'
-- Equation name is 'count3', location is LC2_C3, type is buried.
count3 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = _LC2_C24 & _LC8_C3 & !_LC8_C5 & _LC8_C11;
-- Node name is ':18' = 'count4'
-- Equation name is 'count4', location is LC4_C7, type is buried.
count4 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = _LC2_C7 & _LC3_C7 & !_LC8_C5
# _LC3_C7 & _LC7_C11;
-- Node name is ':17' = 'count5'
-- Equation name is 'count5', location is LC8_C10, type is buried.
count5 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = _LC2_C24 & _LC3_C10;
-- Node name is 'HOput0'
-- Equation name is 'HOput0', type is output
HOput0 = Houtput0;
-- Node name is 'HOput1'
-- Equation name is 'HOput1', type is output
HOput1 = Houtput1;
-- Node name is 'HOput2'
-- Equation name is 'HOput2', type is output
HOput2 = Houtput2;
-- Node name is 'HOput3'
-- Equation name is 'HOput3', type is output
HOput3 = Houtput3;
-- Node name is ':26' = 'Houtput0'
-- Equation name is 'Houtput0', location is LC2_C14, type is buried.
Houtput0 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = !_LC1_C8 & !_LC1_C14 & _LC6_C14
# !_LC1_C14 & _LC6_C24;
-- Node name is ':25' = 'Houtput1'
-- Equation name is 'Houtput1', location is LC5_C14, type is buried.
Houtput1 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = !_LC1_C14 & _LC8_C11 & _LC8_C14
# !_LC1_C14 & _LC6_C24;
-- Node name is ':24' = 'Houtput2'
-- Equation name is 'Houtput2', location is LC8_C22, type is buried.
Houtput2 = DFFE( _EQ009, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = Houtput2 & _LC2_C18 & _LC2_C22 & !_LC6_C19;
-- Node name is ':23' = 'Houtput3'
-- Equation name is 'Houtput3', location is LC1_C22, type is buried.
Houtput3 = DFFE( _EQ010, GLOBAL( CLK), VCC, VCC, VCC);
_EQ010 = Houtput3 & _LC2_C18 & _LC2_C22 & !_LC6_C19;
-- Node name is 'lamp0'
-- Equation name is 'lamp0', type is output
lamp0 = _LC5_C7;
-- Node name is 'lamp1'
-- Equation name is 'lamp1', type is output
lamp1 = _LC1_C7;
-- Node name is 'lamp2'
-- Equation name is 'lamp2', type is output
lamp2 = _LC3_C11;
-- Node name is 'lamp3'
-- Equation name is 'lamp3', type is output
lamp3 = _LC4_C13;
-- Node name is 'lamp4'
-- Equation name is 'lamp4', type is output
lamp4 = _LC1_C10;
-- Node name is 'lamp5'
-- Equation name is 'lamp5', type is output
lamp5 = _LC7_C24;
-- Node name is ':36' = 'light0'
-- Equation name is 'light0', location is LC7_C7, type is buried.
light0 = DFFE( _EQ011, GLOBAL( CLK), VCC, VCC, VCC);
_EQ011 = !_LC4_C10 & _LC6_C7 & !_LC8_C5
# _LC1_C11 & !_LC4_C10;
-- Node name is ':35' = 'light1'
-- Equation name is 'light1', location is LC8_C7, type is buried.
light1 = DFFE( _EQ012, GLOBAL( CLK), VCC, VCC, VCC);
_EQ012 = _LC3_C7 & !_LC8_C5 & light1
# _LC3_C7 & _LC7_C11;
-- Node name is ':34' = 'light2'
-- Equation name is 'light2', location is LC6_C11, type is buried.
light2 = DFFE( _EQ013, GLOBAL( CLK), VCC, VCC, VCC);
_EQ013 = _LC4_C11 & light2
# _LC4_C11 & _LC8_C5
# _LC4_C10;
-- Node name is ':33' = 'light3'
-- Equation name is 'light3', location is LC8_C13, type is buried.
light3 = DFFE( _EQ014, GLOBAL( CLK), VCC, VCC, VCC);
_EQ014 = !_LC1_C14 & _LC7_C13 & _LC8_C11
# !_LC1_C14 & _LC6_C24;
-- Node name is ':32' = 'light4'
-- Equation name is 'light4', location is LC7_C10, type is buried.
light4 = DFFE( _EQ015, GLOBAL( CLK), VCC, VCC, VCC);
_EQ015 = _LC2_C24 & _LC4_C11 & _LC5_C10
# _LC1_C8 & _LC2_C24;
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