📄 decoder.rpt
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INPUT3 : INPUT;
-- Node name is 'output0'
-- Equation name is 'output0', type is output
output0 = _LC1_B9;
-- Node name is 'output1'
-- Equation name is 'output1', type is output
output1 = _LC8_B9;
-- Node name is 'output2'
-- Equation name is 'output2', type is output
output2 = _LC2_B7;
-- Node name is 'output3'
-- Equation name is 'output3', type is output
output3 = _LC3_B9;
-- Node name is 'output4'
-- Equation name is 'output4', type is output
output4 = _LC1_B8;
-- Node name is 'output5'
-- Equation name is 'output5', type is output
output5 = _LC4_B8;
-- Node name is 'output6'
-- Equation name is 'output6', type is output
output6 = _LC6_B8;
-- Node name is ':136'
-- Equation name is '_LC7_B3', type is buried
!_LC7_B3 = _LC7_B3~NOT;
_LC7_B3~NOT = LCELL( _EQ001);
_EQ001 = INPUT2
# INPUT1
# INPUT0
# INPUT3;
-- Node name is ':145'
-- Equation name is '_LC8_B3', type is buried
!_LC8_B3 = _LC8_B3~NOT;
_LC8_B3~NOT = LCELL( _EQ002);
_EQ002 = INPUT2
# INPUT1
# !INPUT0
# INPUT3;
-- Node name is ':154'
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = LCELL( _EQ003);
_EQ003 = !INPUT0 & INPUT1 & !INPUT2 & !INPUT3;
-- Node name is '~163~1'
-- Equation name is '~163~1', location is LC6_B7, type is buried.
-- synthesized logic cell
_LC6_B7 = LCELL( _EQ004);
_EQ004 = INPUT0 & INPUT1 & !INPUT3;
-- Node name is ':172'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = LCELL( _EQ005);
_EQ005 = !INPUT0 & !INPUT1 & INPUT2 & !INPUT3;
-- Node name is ':181'
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = LCELL( _EQ006);
_EQ006 = INPUT0 & !INPUT1 & INPUT2 & !INPUT3;
-- Node name is ':190'
-- Equation name is '_LC5_B3', type is buried
_LC5_B3 = LCELL( _EQ007);
_EQ007 = !INPUT0 & INPUT1 & INPUT2 & !INPUT3;
-- Node name is ':199'
-- Equation name is '_LC4_B7', type is buried
!_LC4_B7 = _LC4_B7~NOT;
_LC4_B7~NOT = LCELL( _EQ008);
_EQ008 = !INPUT2
# !_LC6_B7;
-- Node name is ':208'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = LCELL( _EQ009);
_EQ009 = !INPUT0 & !INPUT1 & !INPUT2 & INPUT3;
-- Node name is ':217'
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = LCELL( _EQ010);
_EQ010 = INPUT0 & !INPUT1 & !INPUT2 & INPUT3;
-- Node name is '~383~1'
-- Equation name is '~383~1', location is LC1_B7, type is buried.
-- synthesized logic cell
_LC1_B7 = LCELL( _EQ011);
_EQ011 = INPUT2 & _LC6_B7
# _LC4_B3
# _LC2_B3;
-- Node name is ':397'
-- Equation name is '_LC7_B8', type is buried
_LC7_B8 = LCELL( _EQ012);
_EQ012 = !_LC5_B3 & _LC6_B8
# _LC1_B7 & !_LC5_B3;
-- Node name is ':409'
-- Equation name is '_LC8_B8', type is buried
_LC8_B8 = LCELL( _EQ013);
_EQ013 = !_LC1_B3 & _LC7_B8
# !_LC1_B3 & _LC6_B3;
-- Node name is ':425'
-- Equation name is '_LC6_B8', type is buried
_LC6_B8 = LCELL( _EQ014);
_EQ014 = !_LC8_B3 & _LC8_B8
# _LC3_B7 & !_LC8_B3
# _LC7_B3;
-- Node name is '~458~1'
-- Equation name is '~458~1', location is LC5_B8, type is buried.
-- synthesized logic cell
_LC5_B8 = LCELL( _EQ015);
_EQ015 = _LC8_B3
# _LC7_B3
# _LC1_B3
# _LC3_B7;
-- Node name is ':458'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = LCELL( _EQ016);
_EQ016 = !_LC2_B8 & _LC4_B8
# _LC1_B7 & !_LC2_B8
# _LC5_B8;
-- Node name is '~482~1'
-- Equation name is '~482~1', location is LC5_B7, type is buried.
-- synthesized logic cell
!_LC5_B7 = _LC5_B7~NOT;
_LC5_B7~NOT = LCELL( _EQ017);
_EQ017 = INPUT2 & !_LC1_B3 & !_LC6_B3
# !_LC1_B3 & !_LC6_B3 & !_LC6_B7;
-- Node name is ':482'
-- Equation name is '_LC3_B8', type is buried
_LC3_B8 = LCELL( _EQ018);
_EQ018 = _LC1_B8
# _LC1_B7
# _LC5_B7
# _LC5_B3;
-- Node name is ':491'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = LCELL( _EQ019);
_EQ019 = _LC8_B3
# _LC7_B3
# !_LC3_B3 & _LC3_B8;
-- Node name is ':500'
-- Equation name is '_LC6_B9', type is buried
_LC6_B9 = LCELL( _EQ020);
_EQ020 = !_LC2_B3 & _LC3_B9
# _LC4_B3;
-- Node name is ':517'
-- Equation name is '_LC7_B9', type is buried
_LC7_B9 = LCELL( _EQ021);
_EQ021 = !_LC1_B3 & !_LC4_B7 & _LC6_B9
# !_LC1_B3 & _LC2_B8;
-- Node name is ':524'
-- Equation name is '_LC3_B9', type is buried
_LC3_B9 = LCELL( _EQ022);
_EQ022 = _LC7_B9 & !_LC8_B3
# _LC3_B7 & !_LC8_B3
# _LC7_B3;
-- Node name is ':533'
-- Equation name is '_LC7_B7', type is buried
_LC7_B7 = LCELL( _EQ023);
_EQ023 = !_LC2_B3 & _LC2_B7
# _LC4_B3;
-- Node name is ':553'
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = LCELL( _EQ024);
_EQ024 = !_LC4_B7 & !_LC5_B7 & _LC7_B7
# _LC5_B3 & !_LC5_B7;
-- Node name is ':557'
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = LCELL( _EQ025);
_EQ025 = !_LC8_B3 & _LC8_B7
# _LC3_B3 & !_LC8_B3
# _LC7_B3;
-- Node name is ':566'
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = LCELL( _EQ026);
_EQ026 = _LC8_B9
# _LC4_B3
# _LC2_B3;
-- Node name is '~578~1'
-- Equation name is '~578~1', location is LC2_B8, type is buried.
-- synthesized logic cell
_LC2_B8 = LCELL( _EQ027);
_EQ027 = _LC5_B3
# _LC6_B3;
-- Node name is ':578'
-- Equation name is '_LC5_B9', type is buried
_LC5_B9 = LCELL( _EQ028);
_EQ028 = _LC1_B10 & !_LC4_B7
# _LC2_B8
# _LC1_B3;
-- Node name is ':590'
-- Equation name is '_LC8_B9', type is buried
_LC8_B9 = LCELL( _EQ029);
_EQ029 = !_LC3_B7 & _LC5_B9 & !_LC8_B3
# _LC7_B3;
-- Node name is ':607'
-- Equation name is '_LC2_B9', type is buried
_LC2_B9 = LCELL( _EQ030);
_EQ030 = _LC1_B9 & !_LC4_B7
# _LC4_B3 & !_LC4_B7
# _LC2_B3 & !_LC4_B7;
-- Node name is '~617~1'
-- Equation name is '~617~1', location is LC3_B7, type is buried.
-- synthesized logic cell
_LC3_B7 = LCELL( _EQ031);
_EQ031 = _LC3_B3
# !INPUT2 & _LC6_B7;
-- Node name is '~617~2'
-- Equation name is '~617~2', location is LC4_B9, type is buried.
-- synthesized logic cell
_LC4_B9 = LCELL( _EQ032);
_EQ032 = _LC2_B8
# _LC1_B3
# _LC3_B7;
-- Node name is ':623'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = LCELL( _EQ033);
_EQ033 = _LC2_B9 & !_LC7_B3 & !_LC8_B3
# _LC4_B9 & !_LC7_B3 & !_LC8_B3;
Project Information d:\maxplus programme\lessondesign1\decoder.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,459K
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