📄 lessondesign.rpt
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- 4 - D 24 OR2 1 3 0 1 |COUNTER:29|:4399
- 6 - D 24 OR2 1 3 0 1 |COUNTER:29|:4429
- 2 - D 19 AND2 s 0 2 0 6 |COUNTER:29|~4431~1
- 1 - F 08 AND2 s 0 2 0 1 |COUNTER:29|~4458~1
- 2 - F 08 OR2 s 0 3 0 2 |COUNTER:29|~4458~2
- 3 - F 21 AND2 s 0 3 0 2 |COUNTER:29|~4458~3
- 6 - F 21 AND2 s 0 3 0 1 |COUNTER:29|~4458~4
- 4 - F 21 AND2 s 0 4 0 3 |COUNTER:29|~4458~5
- 4 - D 19 AND2 s 0 4 0 2 |COUNTER:29|~4458~6
- 6 - D 18 OR2 0 3 0 1 |COUNTER:29|:4483
- 8 - D 18 OR2 0 4 0 1 |COUNTER:29|:4510
- 6 - D 23 OR2 0 3 0 1 |COUNTER:29|:4531
- 6 - F 23 OR2 s 1 3 0 1 |COUNTER:29|~4557~1
- 8 - D 24 OR2 0 2 0 1 |COUNTER:29|:4567
- 1 - D 18 AND2 s 0 2 0 5 |COUNTER:29|~4581~1
- 1 - D 20 AND2 s ! 0 2 0 4 |COUNTER:29|~4603~1
- 4 - D 22 AND2 s 0 2 0 4 |COUNTER:29|~4626~1
- 1 - D 19 AND2 s 0 2 0 2 |COUNTER:29|~4626~2
- 7 - D 19 AND2 s 0 2 0 1 |COUNTER:29|~4638~1
- 7 - D 15 AND2 ! 1 1 0 1 |COUNTER:29|:4874
- 2 - C 21 AND2 0 4 0 6 |DECODER:2|:136
- 8 - C 21 OR2 ! 0 4 0 5 |DECODER:2|:145
- 6 - C 21 AND2 0 4 0 3 |DECODER:2|:154
- 1 - C 21 AND2 s 0 3 0 5 |DECODER:2|~163~1
- 3 - C 21 OR2 ! 0 4 0 5 |DECODER:2|:172
- 7 - C 21 AND2 0 4 0 4 |DECODER:2|:181
- 4 - C 21 OR2 ! 0 4 0 4 |DECODER:2|:190
- 2 - C 15 AND2 0 2 0 5 |DECODER:2|:199
- 5 - C 21 AND2 0 4 0 3 |DECODER:2|:208
- 5 - C 15 AND2 0 4 0 3 |DECODER:2|:217
- 3 - C 15 OR2 s 0 2 0 5 |DECODER:2|~383~1
- 4 - C 13 OR2 0 3 0 1 |DECODER:2|:383
- 5 - C 13 OR2 0 4 0 1 |DECODER:2|:409
- 1 - C 17 OR2 s 0 3 0 4 |DECODER:2|~413~1
- 7 - C 13 OR2 0 4 0 2 |DECODER:2|:425
- 4 - C 18 OR2 0 4 0 1 |DECODER:2|:448
- 3 - C 18 OR2 0 4 0 2 |DECODER:2|:458
- 2 - C 18 OR2 s 0 3 0 2 |DECODER:2|~482~1
- 1 - C 18 OR2 s 0 4 0 1 |DECODER:2|~482~2
- 4 - C 17 OR2 0 3 0 1 |DECODER:2|:491
- 6 - C 15 OR2 0 3 0 1 |DECODER:2|:500
- 7 - C 15 OR2 0 4 0 1 |DECODER:2|:517
- 8 - C 15 OR2 0 4 0 2 |DECODER:2|:524
- 4 - C 15 OR2 0 4 0 1 |DECODER:2|:541
- 3 - C 13 OR2 0 4 0 1 |DECODER:2|:553
- 5 - C 17 OR2 0 4 0 2 |DECODER:2|:557
- 6 - C 18 OR2 0 4 0 1 |DECODER:2|:574
- 7 - C 18 OR2 0 4 0 2 |DECODER:2|:590
- 1 - C 20 OR2 s ! 0 2 0 2 |DECODER:2|~592~1
- 3 - C 17 OR2 0 4 0 1 |DECODER:2|:607
- 2 - C 13 AND2 s ! 0 2 0 3 |DECODER:2|~617~1
- 1 - C 13 OR2 s 0 3 0 2 |DECODER:2|~617~2
- 6 - C 17 OR2 0 4 0 2 |DECODER:2|:623
- 2 - C 17 OR2 s ! 0 2 0 2 |DECODER:2|~625~1
- 6 - B 21 AND2 0 4 0 6 |DECODER:5|:136
- 3 - B 21 OR2 ! 0 4 0 5 |DECODER:5|:145
- 7 - B 21 AND2 0 4 0 3 |DECODER:5|:154
- 3 - B 24 AND2 s 0 3 0 5 |DECODER:5|~163~1
- 8 - B 21 OR2 ! 0 4 0 5 |DECODER:5|:172
- 2 - B 21 AND2 0 4 0 4 |DECODER:5|:181
- 1 - B 21 OR2 ! 0 4 0 4 |DECODER:5|:190
- 4 - B 24 AND2 0 2 0 5 |DECODER:5|:199
- 5 - B 21 AND2 0 4 0 3 |DECODER:5|:208
- 4 - B 21 AND2 0 4 0 3 |DECODER:5|:217
- 2 - B 17 OR2 s 0 2 0 5 |DECODER:5|~383~1
- 1 - B 23 OR2 0 3 0 1 |DECODER:5|:383
- 3 - B 23 OR2 0 4 0 1 |DECODER:5|:409
- 2 - B 24 OR2 s 0 3 0 4 |DECODER:5|~413~1
- 2 - B 23 OR2 0 4 0 2 |DECODER:5|:425
- 3 - B 14 OR2 0 4 0 1 |DECODER:5|:448
- 4 - B 14 OR2 0 4 0 2 |DECODER:5|:458
- 1 - B 24 OR2 s 0 3 0 2 |DECODER:5|~482~1
- 4 - B 17 OR2 s 0 4 0 1 |DECODER:5|~482~2
- 1 - B 17 OR2 0 3 0 1 |DECODER:5|:491
- 5 - B 14 OR2 0 3 0 1 |DECODER:5|:500
- 6 - B 14 OR2 0 4 0 1 |DECODER:5|:517
- 7 - B 14 OR2 0 4 0 2 |DECODER:5|:524
- 5 - B 17 OR2 0 4 0 1 |DECODER:5|:541
- 6 - B 17 OR2 0 4 0 1 |DECODER:5|:553
- 7 - B 17 OR2 0 4 0 2 |DECODER:5|:557
- 6 - B 23 OR2 0 4 0 1 |DECODER:5|:574
- 5 - B 23 OR2 0 4 0 2 |DECODER:5|:590
- 1 - B 18 OR2 s ! 0 2 0 2 |DECODER:5|~592~1
- 7 - B 23 OR2 0 4 0 1 |DECODER:5|:607
- 2 - B 15 AND2 s ! 0 2 0 3 |DECODER:5|~617~1
- 4 - B 23 OR2 s 0 3 0 2 |DECODER:5|~617~2
- 8 - B 23 OR2 0 4 0 2 |DECODER:5|:623
- 1 - B 13 OR2 s ! 0 2 0 2 |DECODER:5|~625~1
- 6 - D 15 AND2 s 0 4 0 1 |LIGHTS:3|~111~1
- 5 - D 15 OR2 s 0 2 0 2 |LIGHTS:3|~111~2
- 8 - D 23 OR2 s 1 2 0 2 |LIGHTS:3|~124~1
- 1 - D 23 OR2 ! 0 4 0 4 |LIGHTS:3|:124
- 2 - D 23 OR2 ! 0 4 0 4 |LIGHTS:3|:137
- 8 - D 15 AND2 s 0 4 0 2 |LIGHTS:3|~150~1
- 1 - D 15 AND2 0 3 0 5 |LIGHTS:3|:150
- 2 - D 15 AND2 0 3 0 5 |LIGHTS:3|:163
- 1 - D 16 AND2 s 0 2 0 1 |LIGHTS:3|~281~1
- 3 - D 15 OR2 s 1 3 0 4 |LIGHTS:3|~285~1
- 3 - D 16 OR2 0 3 1 0 |LIGHTS:3|:285
- 2 - D 13 OR2 1 3 0 1 |LIGHTS:3|:297
- 3 - D 13 AND2 0 3 1 1 |LIGHTS:3|:306
- 1 - D 13 AND2 s 0 3 0 2 |LIGHTS:3|~323~1
- 2 - D 16 OR2 0 3 1 0 |LIGHTS:3|:327
- 4 - D 16 OR2 s ! 0 2 0 1 |LIGHTS:3|~341~1
- 7 - D 13 OR2 0 3 1 0 |LIGHTS:3|:348
- 6 - D 13 OR2 1 2 1 0 |LIGHTS:3|:369
- 8 - D 13 AND2 s 0 2 0 1 |LIGHTS:3|~371~1
- 5 - D 13 OR2 0 3 1 0 |LIGHTS:3|:390
- 4 - D 13 OR2 s ! 0 3 0 3 |LIGHTS:3|~392~1
- 6 - C 13 DFFE + 0 4 1 1 |SCAN:4|:16
- 2 - B 14 DFFE + 0 4 1 1 |SCAN:4|:18
- 6 - A 15 DFFE + 0 4 1 1 |SCAN:4|:20
- 1 - C 15 DFFE + 0 4 1 1 |SCAN:4|:22
- 3 - B 17 DFFE + 0 4 1 1 |SCAN:4|:24
- 5 - C 18 DFFE + 0 4 1 1 |SCAN:4|:26
- 8 - C 17 DFFE + 0 4 1 1 |SCAN:4|:28
- 3 - A 15 DFFE + 0 2 1 0 |SCAN:4|:30
- 8 - A 15 DFFE + 0 2 1 0 |SCAN:4|:32
- 1 - A 15 DFFE + 0 1 0 16 |SCAN:4|count1 (|SCAN:4|:34)
- 2 - A 15 DFFE + 0 0 0 17 |SCAN:4|count0 (|SCAN:4|:35)
- 8 - C 13 OR2 0 4 0 1 |SCAN:4|:204
- 8 - B 14 OR2 0 4 0 1 |SCAN:4|:213
- 4 - A 15 OR2 0 4 0 1 |SCAN:4|:222
- 1 - B 14 OR2 0 4 0 1 |SCAN:4|:231
- 8 - B 17 OR2 0 4 0 1 |SCAN:4|:240
- 8 - C 18 OR2 0 4 0 1 |SCAN:4|:249
- 7 - C 17 OR2 0 4 0 1 |SCAN:4|:258
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\max+plusii learning\course and others\lessondesign4\lessondesign\lessondesign.rpt
lessondesign
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 8/ 96( 8%) 0/ 48( 0%) 17/ 48( 35%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 10/ 96( 10%) 0/ 48( 0%) 19/ 48( 39%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 15/ 96( 15%) 0/ 48( 0%) 32/ 48( 66%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
E: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
F: 36/ 96( 37%) 14/ 48( 29%) 32/ 48( 66%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
14: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 6/24( 25%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 7/24( 29%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\max+plusii learning\course and others\lessondesign4\lessondesign\lessondesign.rpt
lessondesign
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 CLK_Low
INPUT 11 CLk_High
Device-Specific Information:e:\max+plusii learning\course and others\lessondesign4\lessondesign\lessondesign.rpt
lessondesign
** EQUATIONS **
CLk_High : INPUT;
CLK_Low : INPUT;
CLK_normal : INPUT;
Emergency : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC6_C13;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC2_B14;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = _LC6_A15;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC1_C15;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = _LC3_B17;
-- Node name is 'EWG'
-- Equation name is 'EWG', type is output
EWG = _LC2_D16;
-- Node name is 'EWR'
-- Equation name is 'EWR', type is output
EWR = _LC3_D16;
-- Node name is 'EWY'
-- Equation name is 'EWY', type is output
EWY = _LC3_D13;
-- Node name is 'f'
-- Equation name is 'f', type is output
f = _LC5_C18;
-- Node name is 'g'
-- Equation name is 'g', type is output
g = _LC8_C17;
-- Node name is 'Hcontrol'
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