📄 lessondesign.rpt
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Project Informatione:\max+plusii learning\course and others\lessondesign4\lessondesign\lessondesign.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/29/2005 16:17:35
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
lessondesign
EPF10K20TC144-3 4 15 0 0 0 % 258 22 %
User Pins: 4 15 0
Project Informatione:\max+plusii learning\course and others\lessondesign4\lessondesign\lessondesign.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
lessondesign@51 a
lessondesign@49 b
lessondesign@48 c
lessondesign@125 CLk_High
lessondesign@122 CLK_Low
lessondesign@128 CLK_normal
lessondesign@47 d
lessondesign@46 e
lessondesign@86 Emergency
lessondesign@18 EWG
lessondesign@20 EWR
lessondesign@19 EWY
lessondesign@44 f
lessondesign@43 g
lessondesign@102 Hcontrol
lessondesign@8 Lcontrol
lessondesign@21 SNG
lessondesign@23 SNR
lessondesign@22 SNY
Project Informatione:\max+plusii learning\course and others\lessondesign4\lessondesign\lessondesign.rpt
** FILE HIERARCHY **
|decoder:5|
|decoder:2|
|lights:3|
|scan:4|
|scan:4|lpm_add_sub:70|
|scan:4|lpm_add_sub:70|addcore:adder|
|scan:4|lpm_add_sub:70|altshift:result_ext_latency_ffs|
|scan:4|lpm_add_sub:70|altshift:carry_ext_latency_ffs|
|scan:4|lpm_add_sub:70|altshift:oflow_ext_latency_ffs|
|counter:29|
|counter:29|lpm_add_sub:1000|
|counter:29|lpm_add_sub:1000|addcore:adder|
|counter:29|lpm_add_sub:1000|altshift:result_ext_latency_ffs|
|counter:29|lpm_add_sub:1000|altshift:carry_ext_latency_ffs|
|counter:29|lpm_add_sub:1000|altshift:oflow_ext_latency_ffs|
|show:39|
Device-Specific Information:e:\max+plusii learning\course and others\lessondesign4\lessondesign\lessondesign.rpt
lessondesign
***** Logic for device 'lessondesign' compiled without errors.
Device: EPF10K20TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
C
L
R R R R R R R R R R R R R K C R R R R R R R R R R R R
E E E E E E E E E E E E E _ L C E E E E E E E E E E E E
S S S S S S S S S S S S S n G G k G V L S S S S S S S S S S S S
E E E E E G E E E E V E E E E G o N N _ N C K E E E E E E V E E E E E E
R R R R R N R R R R C R R R R N r D D H D C _ R R R R R R C R R R R R R
V V V V V D V V V V C V V V V D m I I i I I L V V V V V V C V V V V V V
E E E E E I E E E E I E E E E I a N N g N N o E E E E E E I E E E E E E
D D D D D O D D D D O D D D D O l T T h T T w D D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | Hcontrol
Lcontrol | 8 101 | RESERVED
RESERVED | 9 100 | RESERVED
RESERVED | 10 99 | RESERVED
RESERVED | 11 98 | RESERVED
RESERVED | 12 97 | RESERVED
RESERVED | 13 96 | RESERVED
RESERVED | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | RESERVED
EWG | 18 91 | RESERVED
EWY | 19 EPF10K20TC144-3 90 | RESERVED
EWR | 20 89 | RESERVED
SNG | 21 88 | RESERVED
SNY | 22 87 | RESERVED
SNR | 23 86 | Emergency
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | RESERVED
RESERVED | 27 82 | RESERVED
RESERVED | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R g f V e d c b G a V V G G G G G R R V R R R R G R R R R V R
E E E N E E C N C C N N N N N E E C E E E E N E E E E C E
S S S D S S C D C C D D D D D S S C S S S S D S S S S C S
E E E I E E I I I I I I I I I E E I E E E E I E E E E I E
R R R O R R O O N N N N N N N R R O R R R R O R R R R O R
V V V V V T T T T T T T V V V V V V V V V V V
E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\max+plusii learning\course and others\lessondesign4\lessondesign\lessondesign.rpt
lessondesign
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A15 6/ 8( 75%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 2/22( 9%)
B13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B14 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 14/22( 63%)
B15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B17 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 14/22( 63%)
B18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B21 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
B23 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 12/22( 54%)
B24 4/ 8( 50%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
C13 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 13/22( 59%)
C15 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 15/22( 68%)
C17 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
C18 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
C20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C21 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
D13 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
D15 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
D16 4/ 8( 50%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
D18 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 16/22( 72%)
D19 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
D20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
D22 6/ 8( 75%) 2/ 8( 25%) 6/ 8( 75%) 0/2 0/2 4/22( 18%)
D23 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 12/22( 54%)
D24 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
F2 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 13/22( 59%)
F4 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
F5 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
F7 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
F8 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
F10 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
F11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
F13 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 9/22( 40%)
F14 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 10/22( 45%)
F15 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 14/22( 63%)
F18 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
F19 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 14/22( 63%)
F20 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
F21 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
F22 7/ 8( 87%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
F23 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 0/2 0/2 12/22( 54%)
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