📄 scan.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY scan IS
PORT(
CLK : IN STD_LOGIC;
Hinput : IN STD_LOGIC_VECTOR( 6 DOWNTO 0);
Linput : IN STD_LOGIC_VECTOR( 6 DOWNTO 0);
Zoput : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0);
Hoput : OUT STD_LOGIC;
LOPUT : OUT STD_LOGIC
);
END scan;
ARCHITECTURE scan_arch OF scan is
SIGNAL count : UNSIGNED( 1 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF( CLK'event and CLK = '1' ) THEN
count <= count + 1;
IF( COUNT = 0 ) THEN
Hoput <= '1'; Loput <= '0'; Zoput <= Hinput;
ELSIF( COUNT = 1 ) THEN
Hoput <= '0'; Loput <= '1'; Zoput <= Linput;
COUNT <= "00";
END IF;
END IF;
END PROCESS;
END scan_arch;
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