📄 lights.rpt
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05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus programme\lessondesign1\lights.rpt
lights
** EQUATIONS **
CLK : INPUT;
input0 : INPUT;
input1 : INPUT;
input2 : INPUT;
input3 : INPUT;
input4 : INPUT;
input5 : INPUT;
-- Node name is 'EWG'
-- Equation name is 'EWG', type is output
EWG = _LC4_C13;
-- Node name is 'EWR'
-- Equation name is 'EWR', type is output
EWR = _LC3_C13;
-- Node name is 'EWY'
-- Equation name is 'EWY', type is output
EWY = _LC7_C23;
-- Node name is 'SNG'
-- Equation name is 'SNG', type is output
SNG = _LC5_C23;
-- Node name is 'SNR'
-- Equation name is 'SNR', type is output
SNR = _LC1_C13;
-- Node name is 'SNY'
-- Equation name is 'SNY', type is output
SNY = _LC1_C23;
-- Node name is '~98~1'
-- Equation name is '~98~1', location is LC1_C20, type is buried.
-- synthesized logic cell
!_LC1_C20 = _LC1_C20~NOT;
_LC1_C20~NOT = LCELL( _EQ001);
_EQ001 = input4
# input3
# input2;
-- Node name is ':111'
-- Equation name is '_LC7_C20', type is buried
!_LC7_C20 = _LC7_C20~NOT;
_LC7_C20~NOT = LCELL( _EQ002);
_EQ002 = _LC5_C20
# input3
# !input5
# input4;
-- Node name is ':124'
-- Equation name is '_LC3_C20', type is buried
!_LC3_C20 = _LC3_C20~NOT;
_LC3_C20~NOT = LCELL( _EQ003);
_EQ003 = input4
# !input3
# input5
# _LC5_C20;
-- Node name is '~137~1'
-- Equation name is '~137~1', location is LC5_C20, type is buried.
-- synthesized logic cell
_LC5_C20 = LCELL( _EQ004);
_EQ004 = input0
# input1
# !input2;
-- Node name is '~137~2'
-- Equation name is '~137~2', location is LC6_C20, type is buried.
-- synthesized logic cell
_LC6_C20 = LCELL( _EQ005);
_EQ005 = input0
# input1;
-- Node name is ':137'
-- Equation name is '_LC4_C20', type is buried
!_LC4_C20 = _LC4_C20~NOT;
_LC4_C20~NOT = LCELL( _EQ006);
_EQ006 = input5
# !input4
# _LC5_C20
# input3;
-- Node name is ':150'
-- Equation name is '_LC3_C23', type is buried
_LC3_C23 = LCELL( _EQ007);
_EQ007 = input0 & !input1 & input5 & _LC1_C20;
-- Node name is ':163'
-- Equation name is '_LC4_C23', type is buried
!_LC4_C23 = _LC4_C23~NOT;
_LC4_C23~NOT = LCELL( _EQ008);
_EQ008 = input0
# !input1
# !input5
# !_LC1_C20;
-- Node name is '~261~1'
-- Equation name is '~261~1', location is LC2_C23, type is buried.
-- synthesized logic cell
!_LC2_C23 = _LC2_C23~NOT;
_LC2_C23~NOT = LCELL( _EQ009);
_EQ009 = !_LC3_C23 & !_LC4_C23;
-- Node name is '~281~1'
-- Equation name is '~281~1', location is LC6_C13, type is buried.
-- synthesized logic cell
_LC6_C13 = LCELL( _EQ010);
_EQ010 = !_LC3_C20 & !_LC4_C20;
-- Node name is ':285'
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = LCELL( _EQ011);
_EQ011 = _LC3_C13 & _LC6_C13
# _LC2_C23 & _LC6_C13
# !_LC2_C20;
-- Node name is ':297'
-- Equation name is '_LC8_C23', type is buried
_LC8_C23 = LCELL( _EQ012);
_EQ012 = !_LC2_C23 & !_LC4_C20 & _LC7_C23
# CLK & _LC4_C20;
-- Node name is '~299~1'
-- Equation name is '~299~1', location is LC5_C13, type is buried.
-- synthesized logic cell
_LC5_C13 = LCELL( _EQ013);
_EQ013 = !_LC2_C23 & !_LC4_C20;
-- Node name is ':306'
-- Equation name is '_LC7_C23', type is buried
_LC7_C23 = LCELL( _EQ014);
_EQ014 = _LC2_C20 & !_LC3_C20 & _LC8_C23;
-- Node name is ':327'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = LCELL( _EQ015);
_EQ015 = _LC2_C20 & _LC4_C13 & _LC5_C13
# _LC2_C20 & _LC3_C20;
-- Node name is '~348~1'
-- Equation name is '~348~1', location is LC2_C13, type is buried.
-- synthesized logic cell
!_LC2_C13 = _LC2_C13~NOT;
_LC2_C13~NOT = LCELL( _EQ016);
_EQ016 = _LC2_C20 & !_LC3_C20 & !_LC4_C20;
-- Node name is ':348'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = LCELL( _EQ017);
_EQ017 = _LC1_C13 & !_LC2_C23
# _LC2_C13;
-- Node name is ':369'
-- Equation name is '_LC1_C23', type is buried
_LC1_C23 = LCELL( _EQ018);
_EQ018 = _LC1_C23 & !_LC4_C23 & _LC6_C23
# CLK & _LC4_C23 & _LC6_C23;
-- Node name is '~371~1'
-- Equation name is '~371~1', location is LC6_C23, type is buried.
-- synthesized logic cell
_LC6_C23 = LCELL( _EQ019);
_EQ019 = !_LC2_C13 & !_LC3_C23;
-- Node name is ':390'
-- Equation name is '_LC5_C23', type is buried
_LC5_C23 = LCELL( _EQ020);
_EQ020 = !_LC2_C13 & _LC3_C23
# !_LC2_C13 & !_LC4_C23 & _LC5_C23;
-- Node name is '~392~1'
-- Equation name is '~392~1', location is LC2_C20, type is buried.
-- synthesized logic cell
_LC2_C20 = LCELL( _EQ021);
_EQ021 = _LC6_C20 & !_LC7_C20
# input5 & !_LC7_C20
# !_LC1_C20 & !_LC7_C20;
Project Information d:\maxplus programme\lessondesign1\lights.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,915K
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