📄 scan.rpt
字号:
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 6/ 48( 12%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
B: 2/ 96( 2%) 3/ 48( 6%) 0/ 48( 0%) 2/16( 12%) 1/16( 6%) 0/16( 0%)
C: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus programme\lessondesign1\scan.rpt
scan
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 CLK
Device-Specific Information: d:\maxplus programme\lessondesign1\scan.rpt
scan
** EQUATIONS **
CLK : INPUT;
Hinput0 : INPUT;
Hinput1 : INPUT;
Hinput2 : INPUT;
Hinput3 : INPUT;
Hinput4 : INPUT;
Hinput5 : INPUT;
Hinput6 : INPUT;
Linput0 : INPUT;
Linput1 : INPUT;
Linput2 : INPUT;
Linput3 : INPUT;
Linput4 : INPUT;
Linput5 : INPUT;
Linput6 : INPUT;
-- Node name is ':35' = 'count0'
-- Equation name is 'count0', location is LC8_C3, type is buried.
count0 = DFFE(!count0, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':34' = 'count1'
-- Equation name is 'count1', location is LC2_C3, type is buried.
count1 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = !count0 & count1;
-- Node name is 'Hoput'
-- Equation name is 'Hoput', type is output
Hoput = _LC1_C3;
-- Node name is 'LOPUT'
-- Equation name is 'LOPUT', type is output
LOPUT = _LC3_C3;
-- Node name is 'Zoput0'
-- Equation name is 'Zoput0', type is output
Zoput0 = _LC7_C3;
-- Node name is 'Zoput1'
-- Equation name is 'Zoput1', type is output
Zoput1 = _LC5_C3;
-- Node name is 'Zoput2'
-- Equation name is 'Zoput2', type is output
Zoput2 = _LC7_A5;
-- Node name is 'Zoput3'
-- Equation name is 'Zoput3', type is output
Zoput3 = _LC1_A5;
-- Node name is 'Zoput4'
-- Equation name is 'Zoput4', type is output
Zoput4 = _LC3_A5;
-- Node name is 'Zoput5'
-- Equation name is 'Zoput5', type is output
Zoput5 = _LC5_A5;
-- Node name is 'Zoput6'
-- Equation name is 'Zoput6', type is output
Zoput6 = _LC4_B3;
-- Node name is ':16'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = _LC1_B3
# !count0 & !count1 & Hinput6;
-- Node name is ':18'
-- Equation name is '_LC5_A5', type is buried
_LC5_A5 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = _LC8_A5
# !count0 & !count1 & Hinput5;
-- Node name is ':20'
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = _LC6_A5
# !count0 & !count1 & Hinput4;
-- Node name is ':22'
-- Equation name is '_LC1_A5', type is buried
_LC1_A5 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = _LC4_A5
# !count0 & !count1 & Hinput3;
-- Node name is ':24'
-- Equation name is '_LC7_A5', type is buried
_LC7_A5 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = _LC2_A5
# !count0 & !count1 & Hinput2;
-- Node name is ':26'
-- Equation name is '_LC5_C3', type is buried
_LC5_C3 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = _LC6_C3
# !count0 & !count1 & Hinput1;
-- Node name is ':28'
-- Equation name is '_LC7_C3', type is buried
_LC7_C3 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = _LC4_C3
# !count0 & !count1 & Hinput0;
-- Node name is ':30'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = DFFE( _EQ009, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = !count0 & !count1
# !count0 & _LC1_C3
# count1 & _LC1_C3;
-- Node name is ':32'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = DFFE( _EQ010, GLOBAL( CLK), VCC, VCC, VCC);
_EQ010 = count0 & !count1
# count0 & _LC3_C3
# count1 & _LC3_C3;
-- Node name is ':204'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = LCELL( _EQ011);
_EQ011 = count1 & _LC4_B3
# count0 & !count1 & Linput6;
-- Node name is ':213'
-- Equation name is '_LC8_A5', type is buried
_LC8_A5 = LCELL( _EQ012);
_EQ012 = count1 & _LC5_A5
# count0 & !count1 & Linput5;
-- Node name is ':222'
-- Equation name is '_LC6_A5', type is buried
_LC6_A5 = LCELL( _EQ013);
_EQ013 = count1 & _LC3_A5
# count0 & !count1 & Linput4;
-- Node name is ':231'
-- Equation name is '_LC4_A5', type is buried
_LC4_A5 = LCELL( _EQ014);
_EQ014 = count1 & _LC1_A5
# count0 & !count1 & Linput3;
-- Node name is ':240'
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = LCELL( _EQ015);
_EQ015 = count1 & _LC7_A5
# count0 & !count1 & Linput2;
-- Node name is ':249'
-- Equation name is '_LC6_C3', type is buried
_LC6_C3 = LCELL( _EQ016);
_EQ016 = count1 & _LC5_C3
# count0 & !count1 & Linput1;
-- Node name is ':258'
-- Equation name is '_LC4_C3', type is buried
_LC4_C3 = LCELL( _EQ017);
_EQ017 = count1 & _LC7_C3
# count0 & !count1 & Linput0;
Project Information d:\maxplus programme\lessondesign1\scan.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,635K
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