📄 lights.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY lights is
port(
input: IN STD_LOGIC_VECTOR( 5 DOWNTO 0);
EWR, EWY, EWG: OUT STD_LOGIC;
SNR, SNY, SNG: OUT STD_LOGIC;
CLK: IN STD_LOGIC
);
END lights;
ARCHITECTURE lights_arch OF lights IS
BEGIN
PROCESS( CLK )
BEGIN
if( input = "000000" ) then
EWR <= '1'; EWY <= '0'; EWG <= '0';
SNR <= '1'; SNY <= '0'; SNG <= '0';
elsif( input = "100100" ) then
EWR <= '1'; EWY <= '0'; EWG <= '0';
SNR <= '1'; SNY <= '0'; SNG <= '0';
ELSIF( input = "001100" ) THEN
EWR <= '0'; EWY <= '0'; EWG <= '1';
SNR <= '1'; SNY <= '0'; SNG <= '0';
ELSIF( input = "010100" ) THEN
EWR <= '0'; EWY <= CLK; EWG <= '0';
SNR <= '1'; SNY <= '0'; SNG <= '0';
ELSIF( input= "100001" ) THEN
EWR <= '1'; EWY <= '0'; EWG <= '0';
SNR <= '0'; SNY <= '0'; SNG <= '1';
ELSIF( input = "100010" ) THEN
EWR <= '1'; EWY <= '0'; EWG <= '0';
SNR <= '0'; SNY <= CLK; SNG <= '0';
END IF;
END PROCESS;
END lights_arch;
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