📄 back_light.rpt
字号:
p = Packed register
Device-Specific Information:e:\maxplus programme\vhdlstduy\lessondesign_2\back_light.rpt
back_light
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\maxplus programme\vhdlstduy\lessondesign_2\back_light.rpt
back_light
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 clk
Device-Specific Information:e:\maxplus programme\vhdlstduy\lessondesign_2\back_light.rpt
back_light
** EQUATIONS **
clk : INPUT;
lights_control0 : INPUT;
lights_control1 : INPUT;
lights_control2 : INPUT;
-- Node name is 'lights0'
-- Equation name is 'lights0', type is output
lights0 = _LC6_A6;
-- Node name is 'lights1'
-- Equation name is 'lights1', type is output
lights1 = _LC5_A6;
-- Node name is 'lights2'
-- Equation name is 'lights2', type is output
lights2 = _LC1_A6;
-- Node name is ':13' = 'presentstate2'
-- Equation name is 'presentstate2', location is LC2_A6, type is buried.
presentstate2 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC5_A9 & presentstate2
# _LC4_A9 & presentstate2
# _LC6_A9 & presentstate2
# !_LC4_A9 & _LC5_A9 & !_LC6_A9 & !presentstate2;
-- Node name is ':12' = 'presentstate10'
-- Equation name is 'presentstate10', location is LC3_A6, type is buried.
presentstate10 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC4_A9 & presentstate10
# _LC6_A9 & presentstate10
# _LC4_A9 & !_LC6_A9 & !presentstate10;
-- Node name is ':11' = 'presentstate11'
-- Equation name is 'presentstate11', location is LC7_A9, type is buried.
presentstate11 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !presentstate10 & presentstate11
# _LC4_A9 & !_LC6_A9 & presentstate10 & !presentstate11
# !_LC4_A9 & presentstate11
# _LC6_A9 & presentstate11;
-- Node name is ':5'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC3_A9 & _LC4_A9 & !_LC6_A9
# !_LC4_A9 & !_LC6_A9 & _LC8_A6;
-- Node name is ':7'
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC1_A9 & !_LC6_A9
# !_LC4_A9 & !_LC6_A9 & _LC7_A6;
-- Node name is ':9'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC4_A9 & !_LC6_A9 & _LC8_A9
# _LC4_A6 & !_LC4_A9 & !_LC6_A9;
-- Node name is ':67'
-- Equation name is '_LC6_A9', type is buried
!_LC6_A9 = _LC6_A9~NOT;
_LC6_A9~NOT = LCELL( _EQ007);
_EQ007 = lights_control2
# lights_control1
# lights_control0;
-- Node name is ':74'
-- Equation name is '_LC4_A9', type is buried
!_LC4_A9 = _LC4_A9~NOT;
_LC4_A9~NOT = LCELL( _EQ008);
_EQ008 = lights_control2
# lights_control1
# !lights_control0;
-- Node name is ':81'
-- Equation name is '_LC5_A9', type is buried
_LC5_A9 = LCELL( _EQ009);
_EQ009 = !lights_control0 & lights_control1 & !lights_control2;
-- Node name is ':88'
-- Equation name is '_LC2_A9', type is buried
_LC2_A9 = LCELL( _EQ010);
_EQ010 = !lights_control0 & !lights_control1 & lights_control2;
-- Node name is ':147'
-- Equation name is '_LC3_A9', type is buried
_LC3_A9 = LCELL( _EQ011);
_EQ011 = !presentstate10 & presentstate11;
-- Node name is ':190'
-- Equation name is '_LC8_A9', type is buried
_LC8_A9 = LCELL( _EQ012);
_EQ012 = !presentstate10
# !presentstate11;
-- Node name is ':317'
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = LCELL( _EQ013);
_EQ013 = _LC4_A9 & !presentstate10 & presentstate11
# _LC4_A9 & presentstate10 & !presentstate11;
-- Node name is ':343'
-- Equation name is '_LC8_A6', type is buried
_LC8_A6 = LCELL( _EQ014);
_EQ014 = _LC1_A6 & !_LC5_A9
# _LC2_A9 & !_LC5_A9
# _LC5_A9 & presentstate2;
-- Node name is ':358'
-- Equation name is '_LC7_A6', type is buried
_LC7_A6 = LCELL( _EQ015);
_EQ015 = _LC5_A9 & presentstate2
# _LC5_A6 & !_LC5_A9
# _LC2_A9 & !_LC5_A9;
-- Node name is ':373'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = LCELL( _EQ016);
_EQ016 = _LC5_A9 & presentstate2
# !_LC5_A9 & _LC6_A6
# _LC2_A9 & !_LC5_A9;
Project Informatione:\maxplus programme\vhdlstduy\lessondesign_2\back_light.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 22,165K
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