📄 car_control.rpt
字号:
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - A 22 LCELL s 1 0 1 0 fro_big_light_con~1
- 8 - C 21 AND2 2 0 1 0 :394
- 2 - C 21 AND2 2 0 1 0 :421
- 4 - C 21 AND2 3 0 1 0 :448
- 5 - C 21 AND2 3 0 1 0 :475
- 3 - C 21 AND2 2 0 1 0 :502
- 6 - C 21 AND2 3 0 1 0 :529
- 7 - C 21 AND2 3 0 1 0 :556
- 1 - C 21 AND2 2 0 1 0 :583
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\maxplus programme\vhdlstduy\lessondesign_2\car_control.rpt
car_control
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\maxplus programme\vhdlstduy\lessondesign_2\car_control.rpt
car_control
** EQUATIONS **
bake : INPUT;
turn_fro_big_light : INPUT;
turn_left : INPUT;
turn_right : INPUT;
-- Node name is 'back_L_lights_con0'
-- Equation name is 'back_L_lights_con0', type is output
back_L_lights_con0 = _LC3_C21;
-- Node name is 'back_L_lights_con1'
-- Equation name is 'back_L_lights_con1', type is output
back_L_lights_con1 = _LC5_C21;
-- Node name is 'back_L_lights_con2'
-- Equation name is 'back_L_lights_con2', type is output
back_L_lights_con2 = _LC4_C21;
-- Node name is 'back_R_lights_con0'
-- Equation name is 'back_R_lights_con0', type is output
back_R_lights_con0 = _LC1_C21;
-- Node name is 'back_R_lights_con1'
-- Equation name is 'back_R_lights_con1', type is output
back_R_lights_con1 = _LC7_C21;
-- Node name is 'back_R_lights_con2'
-- Equation name is 'back_R_lights_con2', type is output
back_R_lights_con2 = _LC6_C21;
-- Node name is 'fro_big_light_con'
-- Equation name is 'fro_big_light_con', type is output
fro_big_light_con = _LC8_A22;
-- Node name is 'fro_big_light_con~1'
-- Equation name is 'fro_big_light_con~1', location is LC8_A22, type is buried.
-- synthesized logic cell
_LC8_A22 = LCELL( turn_fro_big_light);
-- Node name is 'fro_L_light_con'
-- Equation name is 'fro_L_light_con', type is output
fro_L_light_con = _LC8_C21;
-- Node name is 'fro_R_light_con'
-- Equation name is 'fro_R_light_con', type is output
fro_R_light_con = _LC2_C21;
-- Node name is ':394'
-- Equation name is '_LC8_C21', type is buried
_LC8_C21 = LCELL( _EQ001);
_EQ001 = turn_left & !turn_right;
-- Node name is ':421'
-- Equation name is '_LC2_C21', type is buried
_LC2_C21 = LCELL( _EQ002);
_EQ002 = !turn_left & turn_right;
-- Node name is ':448'
-- Equation name is '_LC4_C21', type is buried
_LC4_C21 = LCELL( _EQ003);
_EQ003 = bake & !turn_left & turn_right;
-- Node name is ':475'
-- Equation name is '_LC5_C21', type is buried
_LC5_C21 = LCELL( _EQ004);
_EQ004 = bake & !turn_left & !turn_right;
-- Node name is ':502'
-- Equation name is '_LC3_C21', type is buried
_LC3_C21 = LCELL( _EQ005);
_EQ005 = turn_left & !turn_right;
-- Node name is ':529'
-- Equation name is '_LC6_C21', type is buried
_LC6_C21 = LCELL( _EQ006);
_EQ006 = bake & turn_left & !turn_right;
-- Node name is ':556'
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = LCELL( _EQ007);
_EQ007 = bake & !turn_left & !turn_right;
-- Node name is ':583'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = LCELL( _EQ008);
_EQ008 = !turn_left & turn_right;
Project Informatione:\maxplus programme\vhdlstduy\lessondesign_2\car_control.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,802K
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