📄 car_lights.rpt
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-- Equation name is '_LC1_F17', type is buried
_LC1_F17 = LCELL( _EQ012);
_EQ012 = !_LC1_F13
# !_LC8_F17;
-- Node name is '|BACK_LIGHT:22|:317'
-- Equation name is '_LC3_F17', type is buried
_LC3_F17 = LCELL( _EQ013);
_EQ013 = !_LC1_F13 & _LC4_F17 & _LC8_F17
# _LC1_F13 & _LC4_F17 & !_LC8_F17;
-- Node name is '|BACK_LIGHT:22|:343'
-- Equation name is '_LC6_F13', type is buried
_LC6_F13 = LCELL( _EQ014);
_EQ014 = _LC3_F13 & _LC6_F17
# _LC4_F13 & !_LC6_F17
# _LC2_F17 & !_LC6_F17;
-- Node name is '|BACK_LIGHT:22|:358'
-- Equation name is '_LC7_F13', type is buried
_LC7_F13 = LCELL( _EQ015);
_EQ015 = _LC3_F13 & _LC6_F17
# _LC5_F13 & !_LC6_F17
# _LC2_F17 & !_LC6_F17;
-- Node name is '|BACK_LIGHT:22|:373'
-- Equation name is '_LC8_F13', type is buried
_LC8_F13 = LCELL( _EQ016);
_EQ016 = _LC2_F13 & !_LC6_F17
# _LC2_F17 & !_LC6_F17
# _LC3_F13 & _LC6_F17;
-- Node name is '|BACK_LIGHT:26|:13' = '|BACK_LIGHT:26|presentstate2'
-- Equation name is '_LC3_E22', type is buried
_LC3_E22 = DFFE( _EQ017, clk, VCC, VCC, VCC);
_EQ017 = _LC3_E22 & !_LC6_E20
# _LC3_E22 & _LC5_E20
# _LC3_E22 & _LC7_E20
# !_LC3_E22 & !_LC5_E20 & _LC6_E20 & !_LC7_E20;
-- Node name is '|BACK_LIGHT:26|:12' = '|BACK_LIGHT:26|presentstate10'
-- Equation name is '_LC1_E20', type is buried
_LC1_E20 = DFFE( _EQ018, clk, VCC, VCC, VCC);
_EQ018 = _LC1_E20 & !_LC5_E20
# _LC1_E20 & _LC7_E20
# !_LC1_E20 & _LC5_E20 & !_LC7_E20;
-- Node name is '|BACK_LIGHT:26|:11' = '|BACK_LIGHT:26|presentstate11'
-- Equation name is '_LC3_E20', type is buried
_LC3_E20 = DFFE( _EQ019, clk, VCC, VCC, VCC);
_EQ019 = !_LC1_E20 & _LC3_E20
# _LC1_E20 & !_LC3_E20 & _LC5_E20 & !_LC7_E20
# _LC3_E20 & !_LC5_E20
# _LC3_E20 & _LC7_E20;
-- Node name is '|BACK_LIGHT:26|:5'
-- Equation name is '_LC8_E22', type is buried
_LC8_E22 = DFFE( _EQ020, clk, VCC, VCC, VCC);
_EQ020 = _LC4_E22 & _LC5_E20 & !_LC7_E20
# !_LC5_E20 & _LC5_E22 & !_LC7_E20;
-- Node name is '|BACK_LIGHT:26|:7'
-- Equation name is '_LC2_E22', type is buried
_LC2_E22 = DFFE( _EQ021, clk, VCC, VCC, VCC);
_EQ021 = _LC6_E22 & !_LC7_E20
# !_LC5_E20 & !_LC7_E20 & _LC7_E22;
-- Node name is '|BACK_LIGHT:26|:9'
-- Equation name is '_LC2_E20', type is buried
_LC2_E20 = DFFE( _EQ022, clk, VCC, VCC, VCC);
_EQ022 = _LC5_E20 & !_LC7_E20 & _LC8_E20
# _LC1_E22 & !_LC5_E20 & !_LC7_E20;
-- Node name is '|BACK_LIGHT:26|:67'
-- Equation name is '_LC7_E20', type is buried
!_LC7_E20 = _LC7_E20~NOT;
_LC7_E20~NOT = LCELL( _EQ023);
_EQ023 = _LC1_E14
# _LC2_E14
# _LC3_E14;
-- Node name is '|BACK_LIGHT:26|:74'
-- Equation name is '_LC5_E20', type is buried
!_LC5_E20 = _LC5_E20~NOT;
_LC5_E20~NOT = LCELL( _EQ024);
_EQ024 = _LC1_E14
# _LC2_E14
# !_LC3_E14;
-- Node name is '|BACK_LIGHT:26|:81'
-- Equation name is '_LC6_E20', type is buried
_LC6_E20 = LCELL( _EQ025);
_EQ025 = !_LC1_E14 & _LC2_E14 & !_LC3_E14;
-- Node name is '|BACK_LIGHT:26|:88'
-- Equation name is '_LC4_E20', type is buried
_LC4_E20 = LCELL( _EQ026);
_EQ026 = _LC1_E14 & !_LC2_E14 & !_LC3_E14;
-- Node name is '|BACK_LIGHT:26|:147'
-- Equation name is '_LC4_E22', type is buried
_LC4_E22 = LCELL( _EQ027);
_EQ027 = !_LC1_E20 & _LC3_E20;
-- Node name is '|BACK_LIGHT:26|:190'
-- Equation name is '_LC8_E20', type is buried
_LC8_E20 = LCELL( _EQ028);
_EQ028 = !_LC1_E20
# !_LC3_E20;
-- Node name is '|BACK_LIGHT:26|:317'
-- Equation name is '_LC6_E22', type is buried
_LC6_E22 = LCELL( _EQ029);
_EQ029 = !_LC1_E20 & _LC3_E20 & _LC5_E20
# _LC1_E20 & !_LC3_E20 & _LC5_E20;
-- Node name is '|BACK_LIGHT:26|:343'
-- Equation name is '_LC5_E22', type is buried
_LC5_E22 = LCELL( _EQ030);
_EQ030 = _LC3_E22 & _LC6_E20
# !_LC6_E20 & _LC8_E22
# _LC4_E20 & !_LC6_E20;
-- Node name is '|BACK_LIGHT:26|:358'
-- Equation name is '_LC7_E22', type is buried
_LC7_E22 = LCELL( _EQ031);
_EQ031 = _LC3_E22 & _LC6_E20
# _LC2_E22 & !_LC6_E20
# _LC4_E20 & !_LC6_E20;
-- Node name is '|BACK_LIGHT:26|:373'
-- Equation name is '_LC1_E22', type is buried
_LC1_E22 = LCELL( _EQ032);
_EQ032 = _LC2_E20 & !_LC6_E20
# _LC4_E20 & !_LC6_E20
# _LC3_E22 & _LC6_E20;
-- Node name is '|CAR_CONTROL:1|:394'
-- Equation name is '_LC5_E14', type is buried
_LC5_E14 = LCELL( _EQ033);
_EQ033 = turn_left & !turn_right;
-- Node name is '|CAR_CONTROL:1|:421'
-- Equation name is '_LC4_E14', type is buried
_LC4_E14 = LCELL( _EQ034);
_EQ034 = !turn_left & turn_right;
-- Node name is '|CAR_CONTROL:1|:448'
-- Equation name is '_LC1_E14', type is buried
_LC1_E14 = LCELL( _EQ035);
_EQ035 = bake & !turn_left & turn_right;
-- Node name is '|CAR_CONTROL:1|:475'
-- Equation name is '_LC2_E14', type is buried
_LC2_E14 = LCELL( _EQ036);
_EQ036 = bake & !turn_left & !turn_right;
-- Node name is '|CAR_CONTROL:1|:502'
-- Equation name is '_LC3_E14', type is buried
_LC3_E14 = LCELL( _EQ037);
_EQ037 = turn_left & !turn_right;
-- Node name is '|CAR_CONTROL:1|:529'
-- Equation name is '_LC6_E14', type is buried
_LC6_E14 = LCELL( _EQ038);
_EQ038 = bake & turn_left & !turn_right;
-- Node name is '|CAR_CONTROL:1|:556'
-- Equation name is '_LC7_E14', type is buried
_LC7_E14 = LCELL( _EQ039);
_EQ039 = bake & !turn_left & !turn_right;
-- Node name is '|CAR_CONTROL:1|:583'
-- Equation name is '_LC8_E14', type is buried
_LC8_E14 = LCELL( _EQ040);
_EQ040 = !turn_left & turn_right;
-- Node name is '|FRO_LIGHT:5|:25'
-- Equation name is '_LC2_E16', type is buried
_LC2_E16 = LCELL( _EQ041);
_EQ041 = clk & _LC5_E14;
-- Node name is '|FRO_LIGHT:6|:25'
-- Equation name is '_LC8_E16', type is buried
_LC8_E16 = LCELL( _EQ042);
_EQ042 = clk & _LC4_E14;
Project Informatione:\maxplus programme\vhdlstduy\lessondesign2\lessondesign_2\car_lights.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 33,452K
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