📄 car_lights.rpt
字号:
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
30 - - F -- OUTPUT 0 1 0 0 fro_L_light
21 - - D -- OUTPUT 0 1 0 0 fro_R_light
27 - - E -- OUTPUT 0 1 0 0 L_Big_light
41 - - - 20 OUTPUT 0 1 0 0 L_lights0
39 - - - 21 OUTPUT 0 1 0 0 L_lights1
38 - - - 22 OUTPUT 0 1 0 0 L_lights2
26 - - E -- OUTPUT 0 1 0 0 R_Big_light
12 - - C -- OUTPUT 0 1 0 0 R_lights0
10 - - B -- OUTPUT 0 1 0 0 R_lights1
9 - - B -- OUTPUT 0 1 0 0 R_lights2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\maxplus programme\vhdlstduy\lessondesign2\lessondesign_2\car_lights.rpt
car_lights
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - F 13 DFFE 1 4 1 1 |BACK_LIGHT:22|:5
- 5 - F 13 DFFE 1 4 1 1 |BACK_LIGHT:22|:7
- 2 - F 13 DFFE 1 4 1 1 |BACK_LIGHT:22|:9
- 8 - F 17 DFFE 1 3 0 3 |BACK_LIGHT:22|presentstate11 (|BACK_LIGHT:22|:11)
- 1 - F 13 DFFE 1 2 0 4 |BACK_LIGHT:22|presentstate10 (|BACK_LIGHT:22|:12)
- 3 - F 13 DFFE 1 3 0 3 |BACK_LIGHT:22|presentstate2 (|BACK_LIGHT:22|:13)
- 7 - F 17 OR2 ! 0 3 0 6 |BACK_LIGHT:22|:67
- 4 - F 17 OR2 ! 0 3 0 7 |BACK_LIGHT:22|:74
- 6 - F 17 AND2 0 3 0 4 |BACK_LIGHT:22|:81
- 2 - F 17 AND2 0 3 0 3 |BACK_LIGHT:22|:88
- 5 - F 17 AND2 0 2 0 1 |BACK_LIGHT:22|:147
- 1 - F 17 OR2 0 2 0 1 |BACK_LIGHT:22|:190
- 3 - F 17 OR2 0 3 0 1 |BACK_LIGHT:22|:317
- 6 - F 13 OR2 0 4 0 1 |BACK_LIGHT:22|:343
- 7 - F 13 OR2 0 4 0 1 |BACK_LIGHT:22|:358
- 8 - F 13 OR2 0 4 0 1 |BACK_LIGHT:22|:373
- 8 - E 22 DFFE 1 4 1 1 |BACK_LIGHT:26|:5
- 2 - E 22 DFFE 1 4 1 1 |BACK_LIGHT:26|:7
- 2 - E 20 DFFE 1 4 1 1 |BACK_LIGHT:26|:9
- 3 - E 20 DFFE 1 3 0 3 |BACK_LIGHT:26|presentstate11 (|BACK_LIGHT:26|:11)
- 1 - E 20 DFFE 1 2 0 4 |BACK_LIGHT:26|presentstate10 (|BACK_LIGHT:26|:12)
- 3 - E 22 DFFE 1 3 0 3 |BACK_LIGHT:26|presentstate2 (|BACK_LIGHT:26|:13)
- 7 - E 20 OR2 ! 0 3 0 6 |BACK_LIGHT:26|:67
- 5 - E 20 OR2 ! 0 3 0 7 |BACK_LIGHT:26|:74
- 6 - E 20 AND2 0 3 0 4 |BACK_LIGHT:26|:81
- 4 - E 20 AND2 0 3 0 3 |BACK_LIGHT:26|:88
- 4 - E 22 AND2 0 2 0 1 |BACK_LIGHT:26|:147
- 8 - E 20 OR2 0 2 0 1 |BACK_LIGHT:26|:190
- 6 - E 22 OR2 0 3 0 1 |BACK_LIGHT:26|:317
- 5 - E 22 OR2 0 4 0 1 |BACK_LIGHT:26|:343
- 7 - E 22 OR2 0 4 0 1 |BACK_LIGHT:26|:358
- 1 - E 22 OR2 0 4 0 1 |BACK_LIGHT:26|:373
- 5 - E 14 AND2 2 0 0 1 |CAR_CONTROL:1|:394
- 4 - E 14 AND2 2 0 0 1 |CAR_CONTROL:1|:421
- 1 - E 14 AND2 3 0 0 4 |CAR_CONTROL:1|:448
- 2 - E 14 AND2 3 0 0 4 |CAR_CONTROL:1|:475
- 3 - E 14 AND2 2 0 0 4 |CAR_CONTROL:1|:502
- 6 - E 14 AND2 3 0 0 4 |CAR_CONTROL:1|:529
- 7 - E 14 AND2 3 0 0 4 |CAR_CONTROL:1|:556
- 8 - E 14 AND2 2 0 0 4 |CAR_CONTROL:1|:583
- 2 - E 16 AND2 1 1 1 0 |FRO_LIGHT:5|:25
- 8 - E 16 AND2 1 1 1 0 |FRO_LIGHT:6|:25
- 2 - E 24 LCELL s 1 0 1 0 L_Big_light~1
- 1 - E 24 LCELL s 1 0 1 0 R_Big_light~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\maxplus programme\vhdlstduy\lessondesign2\lessondesign_2\car_lights.rpt
car_lights
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 1/ 96( 1%) 0/ 48( 0%) 1/ 48( 2%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
E: 9/ 96( 9%) 0/ 48( 0%) 12/ 48( 25%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 14/ 48( 29%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 5/24( 20%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\maxplus programme\vhdlstduy\lessondesign2\lessondesign_2\car_lights.rpt
car_lights
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 14 clk
Device-Specific Information:e:\maxplus programme\vhdlstduy\lessondesign2\lessondesign_2\car_lights.rpt
car_lights
** EQUATIONS **
bake : INPUT;
big_light : INPUT;
clk : INPUT;
turn_left : INPUT;
turn_right : INPUT;
-- Node name is 'fro_L_light'
-- Equation name is 'fro_L_light', type is output
fro_L_light = _LC2_E16;
-- Node name is 'fro_R_light'
-- Equation name is 'fro_R_light', type is output
fro_R_light = _LC8_E16;
-- Node name is 'L_Big_light'
-- Equation name is 'L_Big_light', type is output
L_Big_light = _LC2_E24;
-- Node name is 'L_Big_light~1'
-- Equation name is 'L_Big_light~1', location is LC2_E24, type is buried.
-- synthesized logic cell
_LC2_E24 = LCELL( big_light);
-- Node name is 'L_lights0'
-- Equation name is 'L_lights0', type is output
L_lights0 = _LC2_E20;
-- Node name is 'L_lights1'
-- Equation name is 'L_lights1', type is output
L_lights1 = _LC2_E22;
-- Node name is 'L_lights2'
-- Equation name is 'L_lights2', type is output
L_lights2 = _LC8_E22;
-- Node name is 'R_Big_light'
-- Equation name is 'R_Big_light', type is output
R_Big_light = _LC1_E24;
-- Node name is 'R_Big_light~1'
-- Equation name is 'R_Big_light~1', location is LC1_E24, type is buried.
-- synthesized logic cell
_LC1_E24 = LCELL( big_light);
-- Node name is 'R_lights0'
-- Equation name is 'R_lights0', type is output
R_lights0 = _LC2_F13;
-- Node name is 'R_lights1'
-- Equation name is 'R_lights1', type is output
R_lights1 = _LC5_F13;
-- Node name is 'R_lights2'
-- Equation name is 'R_lights2', type is output
R_lights2 = _LC4_F13;
-- Node name is '|BACK_LIGHT:22|:13' = '|BACK_LIGHT:22|presentstate2'
-- Equation name is '_LC3_F13', type is buried
_LC3_F13 = DFFE( _EQ001, clk, VCC, VCC, VCC);
_EQ001 = _LC3_F13 & !_LC6_F17
# _LC3_F13 & _LC4_F17
# _LC3_F13 & _LC7_F17
# !_LC3_F13 & !_LC4_F17 & _LC6_F17 & !_LC7_F17;
-- Node name is '|BACK_LIGHT:22|:12' = '|BACK_LIGHT:22|presentstate10'
-- Equation name is '_LC1_F13', type is buried
_LC1_F13 = DFFE( _EQ002, clk, VCC, VCC, VCC);
_EQ002 = _LC1_F13 & !_LC4_F17
# _LC1_F13 & _LC7_F17
# !_LC1_F13 & _LC4_F17 & !_LC7_F17;
-- Node name is '|BACK_LIGHT:22|:11' = '|BACK_LIGHT:22|presentstate11'
-- Equation name is '_LC8_F17', type is buried
_LC8_F17 = DFFE( _EQ003, clk, VCC, VCC, VCC);
_EQ003 = !_LC1_F13 & _LC8_F17
# _LC1_F13 & _LC4_F17 & !_LC7_F17 & !_LC8_F17
# !_LC4_F17 & _LC8_F17
# _LC7_F17 & _LC8_F17;
-- Node name is '|BACK_LIGHT:22|:5'
-- Equation name is '_LC4_F13', type is buried
_LC4_F13 = DFFE( _EQ004, clk, VCC, VCC, VCC);
_EQ004 = _LC4_F17 & _LC5_F17 & !_LC7_F17
# !_LC4_F17 & _LC6_F13 & !_LC7_F17;
-- Node name is '|BACK_LIGHT:22|:7'
-- Equation name is '_LC5_F13', type is buried
_LC5_F13 = DFFE( _EQ005, clk, VCC, VCC, VCC);
_EQ005 = _LC3_F17 & !_LC7_F17
# !_LC4_F17 & _LC7_F13 & !_LC7_F17;
-- Node name is '|BACK_LIGHT:22|:9'
-- Equation name is '_LC2_F13', type is buried
_LC2_F13 = DFFE( _EQ006, clk, VCC, VCC, VCC);
_EQ006 = _LC1_F17 & _LC4_F17 & !_LC7_F17
# !_LC4_F17 & !_LC7_F17 & _LC8_F13;
-- Node name is '|BACK_LIGHT:22|:67'
-- Equation name is '_LC7_F17', type is buried
!_LC7_F17 = _LC7_F17~NOT;
_LC7_F17~NOT = LCELL( _EQ007);
_EQ007 = _LC6_E14
# _LC7_E14
# _LC8_E14;
-- Node name is '|BACK_LIGHT:22|:74'
-- Equation name is '_LC4_F17', type is buried
!_LC4_F17 = _LC4_F17~NOT;
_LC4_F17~NOT = LCELL( _EQ008);
_EQ008 = _LC6_E14
# _LC7_E14
# !_LC8_E14;
-- Node name is '|BACK_LIGHT:22|:81'
-- Equation name is '_LC6_F17', type is buried
_LC6_F17 = LCELL( _EQ009);
_EQ009 = !_LC6_E14 & _LC7_E14 & !_LC8_E14;
-- Node name is '|BACK_LIGHT:22|:88'
-- Equation name is '_LC2_F17', type is buried
_LC2_F17 = LCELL( _EQ010);
_EQ010 = _LC6_E14 & !_LC7_E14 & !_LC8_E14;
-- Node name is '|BACK_LIGHT:22|:147'
-- Equation name is '_LC5_F17', type is buried
_LC5_F17 = LCELL( _EQ011);
_EQ011 = !_LC1_F13 & _LC8_F17;
-- Node name is '|BACK_LIGHT:22|:190'
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