alert.hier_info

vhdl语言

|alert
clk => count1[0].CLK
clk => lamp[2]~reg0.CLK
clk => lamp[1]~reg0.CLK
clk => lamp[0]~reg0.CLK
clk => count[1].CLK
clk => count[0].CLK
clk => count1[1].CLK
dain[0] => Equal~0.IN13
dain[1] => Equal~0.IN12
dain[2] => Equal~0.IN11
dain[3] => Equal~0.IN10
dain[4] => Equal~0.IN9
dain[5] => Equal~0.IN8
dain[6] => Equal~0.IN7
speak <= count1[1].DB_MAX_OUTPUT_PORT_TYPE
lamp[0] <= lamp[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lamp[1] <= lamp[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lamp[2] <= lamp[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE