clock.map.qmsg

vhdl语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 29 17:46:43 2008 " "Info: Processing started: Wed Oct 29 17:46:43 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "a " "Warning: Pin \"a\" is missing source" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 520 1032 1208 536 "a" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "b " "Warning: Pin \"b\" is missing source" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 536 1032 1208 552 "b" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "c " "Warning: Pin \"c\" is missing source" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 552 1032 1208 568 "c" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "d " "Warning: Pin \"d\" is missing source" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 568 1032 1208 584 "d" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "e " "Warning: Pin \"e\" is missing source" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 584 1032 1208 600 "e" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "f " "Warning: Pin \"f\" is missing source" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 600 1032 1208 616 "f" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "g " "Warning: Pin \"g\" is missing source" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 616 1032 1208 632 "g" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "alert.vhd 2 1 " "Warning: Using design file alert.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alert-fun " "Info: Found design unit 1: alert-fun" {  } { { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 alert " "Info: Found entity 1: alert" {  } { { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alert alert:inst " "Info: Elaborating entity \"alert\" for hierarchy \"alert:inst\"" {  } { { "clock.bdf" "inst" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 120 752 904 216 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count1 alert.vhd(18) " "Warning (10492): VHDL Process Statement warning at alert.vhd(18): signal \"count1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 18 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "minute.vhd 2 1 " "Warning: Using design file minute.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 minute-fun " "Info: Found design unit 1: minute-fun" {  } { { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 minute " "Info: Found entity 1: minute" {  } { { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "minute minute:inst2 " "Info: Elaborating entity \"minute\" for hierarchy \"minute:inst2\"" {  } { { "clock.bdf" "inst2" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 296 416 560 424 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk1 minute.vhd(19) " "Warning (10492): VHDL Process Statement warning at minute.vhd(19): signal \"clk1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "second.vhd 2 1 " "Warning: Using design file second.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 second-fun " "Info: Found design unit 1: second-fun" {  } { { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 second " "Info: Found entity 1: second" {  } { { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "second second:inst3 " "Info: Elaborating entity \"second\" for hierarchy \"second:inst3\"" {  } { { "clock.bdf" "inst3" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 144 416 560 240 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "seltime.vhd 2 1 " "Warning: Using design file seltime.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seltime-fun " "Info: Found design unit 1: seltime-fun" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 seltime " "Info: Found entity 1: seltime" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}