clock_top.map.qmsg

vhdl语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 27 17:07:22 2008 " "Info: Processing started: Mon Oct 27 17:07:22 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock_top -c clock_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock_top -c clock_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock_top-a " "Info: Found design unit 1: clock_top-a" {  } { { "clock_top.vhd" "" { Text "F:/vhdlpjt/clock/clock_top.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock_top " "Info: Found entity 1: clock_top" {  } { { "clock_top.vhd" "" { Text "F:/vhdlpjt/clock/clock_top.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock_top " "Info: Elaborating entity \"clock_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "second.vhd 2 1 " "Warning: Using design file second.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 second-fun " "Info: Found design unit 1: second-fun" {  } { { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 second " "Info: Found entity 1: second" {  } { { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "second second:u1 " "Info: Elaborating entity \"second\" for hierarchy \"second:u1\"" {  } { { "clock_top.vhd" "u1" { Text "F:/vhdlpjt/clock/clock_top.vhd" 74 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "minute.vhd 2 1 " "Warning: Using design file minute.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 minute-fun " "Info: Found design unit 1: minute-fun" {  } { { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 minute " "Info: Found entity 1: minute" {  } { { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "minute minute:u2 " "Info: Elaborating entity \"minute\" for hierarchy \"minute:u2\"" {  } { { "clock_top.vhd" "u2" { Text "F:/vhdlpjt/clock/clock_top.vhd" 80 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk1 minute.vhd(19) " "Warning (10492): VHDL Process Statement warning at minute.vhd(19): signal \"clk1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "hour.vhd 2 1 " "Warning: Using design file hour.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hour-fun " "Info: Found design unit 1: hour-fun" {  } { { "hour.vhd" "" { Text "F:/vhdlpjt/clock/hour.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 hour " "Info: Found entity 1: hour" {  } { { "hour.vhd" "" { Text "F:/vhdlpjt/clock/hour.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hour hour:u3 " "Info: Elaborating entity \"hour\" for hierarchy \"hour:u3\"" {  } { { "clock_top.vhd" "u3" { Text "F:/vhdlpjt/clock/clock_top.vhd" 87 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "alert.vhd 2 1 " "Warning: Using design file alert.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alert-fun " "Info: Found design unit 1: alert-fun" {  } { { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 alert " "Info: Found entity 1: alert" {  } { { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alert alert:u4 " "Info: Elaborating entity \"alert\" for hierarchy \"alert:u4\"" {  } { { "clock_top.vhd" "u4" { Text "F:/vhdlpjt/clock/clock_top.vhd" 91 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count1 alert.vhd(18) " "Warning (10492): VHDL Process Statement warning at alert.vhd(18): signal \"count1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 18 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "seltime.vhd 2 1 " "Warning: Using design file seltime.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seltime-fun " "Info: Found design unit 1: seltime-fun" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 seltime " "Info: Found entity 1: seltime" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seltime seltime:u5 " "Info: Elaborating entity \"seltime\" for hierarchy \"seltime:u5\"" {  } { { "clock_top.vhd" "u5" { Text "F:/vhdlpjt/clock/clock_top.vhd" 96 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}