deled.tan.qmsg

vhdl语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 27 16:12:45 2008 " "Info: Processing started: Mon Oct 27 16:12:45 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off deled -c deled " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off deled -c deled" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "led\[0\]\$latch " "Warning: Node \"led\[0\]\$latch\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "led\[1\]\$latch " "Warning: Node \"led\[1\]\$latch\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "led\[2\]\$latch " "Warning: Node \"led\[2\]\$latch\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "led\[3\]\$latch " "Warning: Node \"led\[3\]\$latch\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "led\[4\]\$latch " "Warning: Node \"led\[4\]\$latch\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "led\[5\]\$latch " "Warning: Node \"led\[5\]\$latch\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "led\[6\]\$latch " "Warning: Node \"led\[6\]\$latch\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NOTHING_TO_TIMING_ANALYZE" "" "Warning: No paths found for timing analysis" {  } {  } 0 0 "No paths found for timing analysis" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 9 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 27 16:12:46 2008 " "Info: Processing ended: Mon Oct 27 16:12:46 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}