clock.tan.rpt

vhdl语言

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Oct 29 17:47:01 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "clkdsp" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "second:inst3|enmin" as buffer
Info: Clock "clk" has Internal fmax of 66.23 MHz between source register "minute:inst2|count[5]" and destination register "alert:inst|count1[0]" (period= 15.1 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A13; Fanout = 8; REG Node = 'minute:inst2|count[5]'
        Info: 2: + IC(2.000 ns) + CELL(1.900 ns) = 3.900 ns; Loc. = LC4_A14; Fanout = 1; COMB Node = 'rtl~144'
        Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 6.400 ns; Loc. = LC7_A14; Fanout = 2; COMB Node = 'rtl~0'
        Info: 4: + IC(0.600 ns) + CELL(1.000 ns) = 8.000 ns; Loc. = LC3_A14; Fanout = 2; REG Node = 'alert:inst|count1[0]'
        Info: Total cell delay = 4.800 ns ( 60.00 % )
        Info: Total interconnect delay = 3.200 ns ( 40.00 % )
    Info: - Smallest clock skew is -4.900 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_A14; Fanout = 2; REG Node = 'alert:inst|count1[0]'
            Info: Total cell delay = 1.900 ns ( 48.72 % )
            Info: Total interconnect delay = 2.000 ns ( 51.28 % )
        Info: - Longest clock path from clock "clk" to source register is 8.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC1_A19; Fanout = 8; REG Node = 'second:inst3|enmin'
            Info: 3: + IC(4.000 ns) + CELL(0.000 ns) = 8.800 ns; Loc. = LC4_A13; Fanout = 8; REG Node = 'minute:inst2|count[5]'
            Info: Total cell delay = 2.800 ns ( 31.82 % )
            Info: Total interconnect delay = 6.000 ns ( 68.18 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Micro setup delay of destination is 1.300 ns
Info: Clock "clkdsp" Internal fmax is restricted to 125.0 MHz between source register "seltime:inst5|count[0]" and destination register "seltime:inst5|count[1]"
    Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C14; Fanout = 4; REG Node = 'seltime:inst5|count[0]'
            Info: 2: + IC(0.600 ns) + CELL(1.400 ns) = 2.000 ns; Loc. = LC1_C14; Fanout = 4; REG Node = 'seltime:inst5|count[1]'
            Info: Total cell delay = 1.400 ns ( 70.00 % )
            Info: Total interconnect delay = 0.600 ns ( 30.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clkdsp" to destination register is 3.900 ns
                Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_1; Fanout = 3; CLK Node = 'clkdsp'
                Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_C14; Fanout = 4; REG Node = 'seltime:inst5|count[1]'
                Info: Total cell delay = 1.900 ns ( 48.72 % )
                Info: Total interconnect delay = 2.000 ns ( 51.28 % )
            Info: - Longest clock path from clock "clkdsp" to source register is 3.900 ns
                Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_1; Fanout = 3; CLK Node = 'clkdsp'
                Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_C14; Fanout = 4; REG Node = 'seltime:inst5|count[0]'
                Info: Total cell delay = 1.900 ns ( 48.72 % )
                Info: Total interconnect delay = 2.000 ns ( 51.28 % )
        Info: + Micro clock to output delay of source is 0.900 ns
        Info: + Micro setup delay of destination is 1.300 ns
Info: tsu for register "second:inst3|count[4]" (data pin = "setmin", clock pin = "clk") is 2.200 ns
    Info: + Longest pin to register delay is 4.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_44; Fanout = 8; PIN Node = 'setmin'
        Info: 2: + IC(1.900 ns) + CELL(1.000 ns) = 4.800 ns; Loc. = LC2_A17; Fanout = 6; REG Node = 'second:inst3|count[4]'
        Info: Total cell delay = 2.900 ns ( 60.42 % )
        Info: Total interconnect delay = 1.900 ns ( 39.58 % )
    Info: + Micro setup delay of destination is 1.300 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_A17; Fanout = 6; REG Node = 'second:inst3|count[4]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: tco from clock "clkdsp" to destination pin "sel[0]" through register "seltime:inst5|count[0]" is 10.000 ns
    Info: + Longest clock path from clock "clkdsp" to source register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_1; Fanout = 3; CLK Node = 'clkdsp'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_C14; Fanout = 4; REG Node = 'seltime:inst5|count[0]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Longest register to pin delay is 5.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C14; Fanout = 4; REG Node = 'seltime:inst5|count[0]'
        Info: 2: + IC(1.300 ns) + CELL(3.900 ns) = 5.200 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'sel[0]'
        Info: Total cell delay = 3.900 ns ( 75.00 % )
        Info: Total interconnect delay = 1.300 ns ( 25.00 % )
Info: th for register "minute:inst2|count[3]" (data pin = "sethour", clock pin = "clk") is 5.200 ns
    Info: + Longest clock path from clock "clk" to destination register is 8.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC1_A19; Fanout = 8; REG Node = 'second:inst3|enmin'
        Info: 3: + IC(4.000 ns) + CELL(0.000 ns) = 8.800 ns; Loc. = LC1_A13; Fanout = 5; REG Node = 'minute:inst2|count[3]'
        Info: Total cell delay = 2.800 ns ( 31.82 % )
        Info: Total interconnect delay = 6.000 ns ( 68.18 % )
    Info: + Micro hold delay of destination is 1.400 ns
    Info: - Shortest pin to register delay is 5.000 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_42; Fanout = 7; PIN Node = 'sethour'
        Info: 2: + IC(2.100 ns) + CELL(1.000 ns) = 5.000 ns; Loc. = LC1_A13; Fanout = 5; REG Node = 'minute:inst2|count[3]'
        Info: Total cell delay = 2.900 ns ( 58.00 % )
        Info: Total interconnect delay = 2.100 ns ( 42.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Oct 29 17:47:02 2008
    Info: Elapsed time: 00:00:02