📄 second.map.rpt
字号:
; -- Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 8 ;
; Total logic cells in carry chains ; 13 ;
; I/O pins ; 11 ;
; Maximum fan-out node ; reset ;
; Maximum fan-out ; 9 ;
; Total fan-out ; 103 ;
; Average fan-out ; 2.51 ;
+-----------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------+
; |second ; 30 (17) ; 8 ; 0 ; 11 ; 22 (9) ; 2 (2) ; 6 (6) ; 13 (0) ; 0 (0) ; |second ;
; |lpm_add_sub:add_rtl_0| ; 6 (0) ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 0 (0) ; 6 (0) ; 0 (0) ; |second|lpm_add_sub:add_rtl_0 ;
; |addcore:adder| ; 6 (1) ; 0 ; 0 ; 0 ; 6 (1) ; 0 (0) ; 0 (0) ; 6 (1) ; 0 (0) ; |second|lpm_add_sub:add_rtl_0|addcore:adder ;
; |a_csnbuffer:result_node| ; 5 (5) ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |second|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:add_rtl_1| ; 7 (0) ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; 0 (0) ; |second|lpm_add_sub:add_rtl_1 ;
; |addcore:adder| ; 7 (1) ; 0 ; 0 ; 0 ; 7 (1) ; 0 (0) ; 0 (0) ; 7 (1) ; 0 (0) ; |second|lpm_add_sub:add_rtl_1|addcore:adder ;
; |a_csnbuffer:result_node| ; 6 (6) ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; |second|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 8 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 7 ;
; Number of registers using Asynchronous Load ; 1 ;
; Number of registers using Clock Enable ; 8 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+---------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH ; 7 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_enh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+---------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH ; 7 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_enh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/vhdlpjt/clock/second.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Tue Oct 28 16:51:36 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off second -c second
Info: Found 2 design units, including 1 entities, in source file second.vhd
Info: Found design unit 1: second-fun
Info: Found entity 1: second
Info: Elaborating entity "second" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Implemented 41 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 8 output pins
Info: Implemented 30 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Oct 28 16:51:38 2008
Info: Elapsed time: 00:00:03
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -