clock_top.tan.summary

vhdl语言

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.400 ns
From           : setmin
To             : second:u1|count[3]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.900 ns
From           : seltime:u5|count[2]
To             : sel[2]
From Clock     : clkdsp
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 6.100 ns
From           : reset
To             : minute:u2|enhour
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 60.61 MHz ( period = 16.500 ns )
From           : minute:u2|count[4]
To             : alert:u4|count1[1]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clkdsp'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : seltime:u5|count[1]
To             : seltime:u5|count[0]
From Clock     : clkdsp
To Clock       : clkdsp
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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