clock_top.map.summary

来自「vhdl语言」· SUMMARY 代码 · 共 9 行

Analysis & Synthesis Status : Successful - Mon Oct 27 17:07:29 2008
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : clock_top
Top-level Entity Name : clock_top
Family : FLEX10K
Total logic elements : 154
Total pins : 20
Total memory bits : 0