hour.sim.rpt

vhdl语言

; Total output ports with no 0-value coverage         ; 3            ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+
; Node Name                                                                      ; Output Port Name                                                               ; Output Port Type ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+
; |hour|count[0]                                                                 ; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0]      ; cout             ;
; |hour|count[1]                                                                 ; |hour|count[1]                                                                 ; data_out0        ;
; |hour|count[2]                                                                 ; |hour|count[2]                                                                 ; data_out0        ;
; |hour|count[3]                                                                 ; |hour|count[3]                                                                 ; data_out0        ;
; |hour|count[4]                                                                 ; |hour|count[4]                                                                 ; data_out0        ;
; |hour|count[5]                                                                 ; |hour|count[5]                                                                 ; data_out0        ;
; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; data_out0        ;
; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1]      ; cout             ;
; |hour|LessThan~33                                                              ; |hour|LessThan~33                                                              ; data_out0        ;
; |hour|rtl~28                                                                   ; |hour|rtl~28                                                                   ; data_out0        ;
; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; data_out0        ;
; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2]      ; cout             ;
; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; data_out0        ;
; |hour|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |hour|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; data_out0        ;
; |hour|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |hour|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4]      ; cout             ;
; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; data_out0        ;
; |hour|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[5]                    ; |hour|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[5]                    ; data_out0        ;
; |hour|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[5]                    ; |hour|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[5]                    ; data_out0        ;
; |hour|count~499                                                                ; |hour|count~499                                                                ; data_out0        ;
; |hour|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3]      ; |hour|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3]      ; cout             ;
; |hour|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2]      ; |hour|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2]      ; cout             ;
; |hour|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1]      ; |hour|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1]      ; cout             ;
; |hour|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0]      ; |hour|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0]      ; cout             ;
; |hour|clk                                                                      ; |hour|clk                                                                      ; dataout          ;
; |hour|daout[0]                                                                 ; |hour|daout[0]                                                                 ; padio            ;
; |hour|daout[1]                                                                 ; |hour|daout[1]                                                                 ; padio            ;
; |hour|daout[2]                                                                 ; |hour|daout[2]                                                                 ; padio            ;
; |hour|daout[3]                                                                 ; |hour|daout[3]                                                                 ; padio            ;
; |hour|daout[4]                                                                 ; |hour|daout[4]                                                                 ; padio            ;
; |hour|daout[5]                                                                 ; |hour|daout[5]                                                                 ; padio            ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                      ;
+--------------------------------------------------------------------------------+---------------------------------------------------------------------------+------------------+
; Node Name                                                                      ; Output Port Name                                                          ; Output Port Type ;
+--------------------------------------------------------------------------------+---------------------------------------------------------------------------+------------------+
; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] ; cout             ;
; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] ; cout             ;
; |hour|reset                                                                    ; |hour|reset                                                               ; dataout          ;
+--------------------------------------------------------------------------------+---------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                                                      ;
+--------------------------------------------------------------------------------+---------------------------------------------------------------------------+------------------+
; Node Name                                                                      ; Output Port Name                                                          ; Output Port Type ;
+--------------------------------------------------------------------------------+---------------------------------------------------------------------------+------------------+
; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] ; cout             ;
; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |hour|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] ; cout             ;
; |hour|reset                                                                    ; |hour|reset                                                               ; dataout          ;
+--------------------------------------------------------------------------------+---------------------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Oct 28 17:08:46 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off hour -c hour
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      90.91 %
Info: Number of transitions in simulation is 1384
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Oct 28 17:08:46 2008
    Info: Elapsed time: 00:00:01