clock_top.vhd

vhdl语言

library ieee;
use ieee.std_logic_1164.all;
entity clock_top is
port (	clk,reset,setmin,sethour,clkdsp:in std_logic;
		speaker:	out std_logic;
		lamp:	out std_logic_vector(2 downto 0);
		sel:	out std_logic_vector(2 downto 0);
		a,b,c,d,e,f,g,dp:	out std_logic);
end clock_top;
--*************************************************
architecture a of clock_top is
--*************************************************
--second counter
COMPONENT second
	PORT(
		clk, reset,setmin: IN	STD_LOGIC;
		daout:	out std_logic_vector(6 downto 0);
		enmin: OUT	STD_LOGIC);
END COMPONENT;
--*************************************************
-- minute counter
COMPONENT minute
	PORT(
		clk, clk1,reset,sethour: IN	STD_LOGIC;
		enhour: OUT	STD_LOGIC;
		daout:	out std_logic_vector(6 downto 0));
END COMPONENT;
--*************************************************
--hour counter
COMPONENT hour
	PORT(
		clk, reset: IN	STD_LOGIC;
		daout:	out std_logic_vector(5 downto 0));
END COMPONENT;
--*************************************************
COMPONENT alert
	PORT(
		clk: IN	STD_LOGIC;
		dain:in std_logic_vector(6 downto 0);
		lamp:	out std_logic_vector(2 downto 0);
		speak: OUT	STD_LOGIC);
END COMPONENT;
--*************************************************
COMPONENT seltime
	PORT(
		clk1, reset: IN	STD_LOGIC;
		sec,min:in std_logic_vector(6 downto 0);
		hour:in std_logic_vector(5 downto 0);
		daout:	out std_logic_vector(3 downto 0);
		sel: OUT	STD_LOGIC_vector(2 downto 0));
END COMPONENT;
--*************************************************
COMPONENT deled
	PORT(
		num: IN	STD_LOGIC_vector(3 downto 0);
		led:	out std_logic_vector(6 downto 0));
END COMPONENT;
--*************************************************
signal ledout:	std_logic_vector(6 downto 0);
signal enmin_re,enhour_re: std_logic;
signal second_daout,minute_daout:std_logic_vector(6 downto 0);
signal hour_daout:std_logic_vector(5 downto 0);
signal seltime_daout:std_logic_vector(3 downto 0);
--*************************************************
begin
a<=ledout(0);
b<=ledout(1);
c<=ledout(2);
d<=ledout(3);
e<=ledout(4);
f<=ledout(5);
g<=ledout(6);
dp<='0';
u1: second port map(
					reset	=>reset,
					clk		=>clk,
					setmin	=>setmin,
					enmin	=>enmin_re,
					daout	=>second_daout);
u2:minute port map(
					clk		=>enmin_re,
					clk1	=>clk,
					reset	=>reset,
					sethour	=>sethour,
					enhour	=>enhour_re,
					daout	=>minute_daout);
u3:hour port map(
					clk		=>enhour_re,
					reset	=>reset,
					daout	=>hour_daout);
u4:alert port map(
					clk		=>clk,
					dain	=>minute_daout,
					speak	=>speaker,
					lamp	=>lamp);
u5:seltime port map(
					clk1	=>clkdsp,
					reset	=>reset,
					sec		=>second_daout,
					min		=>minute_daout,
					hour	=>hour_daout,
					daout	=>seltime_daout,
					sel		=>sel);
u6:deled port map(
					num		=>seltime_daout,
					led		=>ledout);
end a;