cu.v.txt

用vlog语言编写的cpu控制器源代码

module CU (CLE,ZLE,ALU_OP,ACLE,GR_address,GRLE,IRLE,ARLE,PCLE,
PCCE,mux_C_sel,mux_DB_sel,mux_AB_SEL,RW,clk,reset,C_in,Z_in,IR_in);
parameter FIRST='b00,SECOND='b01,THIRD='b10,HLT='b11;
output CLE; reg CLE;
output ZLE; reg ZLE;
output ACLE; reg ACLE;
outpet GRLE; reg GRLE;
output ARLE; reg ARLE;
output IRLE; reg IRLE;
output PCLE; reg PCLE;
output PCCE; reg PCCE;
output [3:0] ALU_OP ;reg[4:0] ALU_OP;
output [2:0] GR_address; reg[2:0] GR_address;
output [1:0] mux_C_sel; reg[1:0] mux_C_sel;
output [1:0] mux_DB_sel; reg[1:0] mux_DB_sel;
output mux_AB_sel; reg mux_AB_sel;
output RW; reg RW;
input clk;
input reset;
input C_in;
input Z_in;
input [7:0] IR_in;
reg [1:0] state;

always@(posedge clk or negedge reset)
begin
if(!reset)
state<=FIRST;
else begin
case(state)
FIRST:state<=SECOND;
SECOND:state<=THIRD;
THIRD:if(IR_in[7:3]=='b01111)
state<=HLT;
else
state<=FIRST;
HLT:state<=HLT;
endcase 
end
end

always@(state or in or Z_in or IR_in)
begin
CLE='b0;
ZLE='b0;
ALU_OP='b0;
ACLE='b0;
GR_address='b0;
GRLE='b0;
IRLE='b0;
ARLE='b0;
PCLE='b0;
PCCE='b0;
mux_C_sel='b0;
mux_DB_sel=2'b0;
mux_AB_sel='b0;
RE='b0;
case(state)
FIRST:begin
mux_AB_sel='b0;
mux_DB_sel='b10;
IRLE='b1;
PCCE='b1;
end
SECOND:begin
case(IR_in[7:3])
'b00000,
'b0 0001:
begin
mux_AB_sel='b0;
mux_DB_sel='b10;
PCCE='b1;
ARLE='b1;
end
'b000 10:begin
GR_address=IR_in[2:0];
ALU_OP=IR_in[7:3];
mux_DB_sel='b01;
//gr_address=IR_in[2:0];
GRLE='b1;
CLE='b1;
ZLE='b1;
end
'b00011, //GR->AC
'b00100, //AC+GR->AC
'b00101, //AC-GR->AC
'b00110, //AC+GR+C->AC
'b00111, //AC-GR-C->AC
'b01000, //and AC,GR
'b01001, //xor AC,GR
'b01010, //SHCR AC,GR
'b01011, //AHCL AC,GR
begin
GR_address=IR_in[2:0];
ALU_OP=IR_in[7:3];
mux_DB_sel='b01;
ACLE='b1;
CLE='b1;
ZLE='b1;
if(IR_in[7:3]=='b01010)
mux_C_sel= 'b10;
if(IR_in[7:3]=='b01011)
mux_C_sel= 'b01;
end
'b01100, //JMP Mi
'b01101, //JNZ Mi
'b01110: //JNC Mi
begin
mux_AB_sel='b0;
mux_DB_sel='b10;
case(IR_in[4:3])
'b00:PCLE='b1;
'b01:begin PCLE= !Z_in;PCCE='b1;end
'b10:begin pcle= !C_in;pcce='b1;end
endcase
endP
endcase
end

THIRD:begin
if(IR_in[7:3]=='b00000  IR_in[7:3]=='b00001)begin
mux_AB_sel='b1;
if(!IR_in[3])
begin
mux_DB_sel='b10;
ACLE='b1;
end
else begin
mux_DB_sel='b00;
RW='b1;
end
end
end
endcase
end 
endmodule