mult8x8.map.qmsg

一个用VerilogHDL语言编写的8X8的乘法器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 23 10:37:39 2006 " "Info: Processing started: Mon Oct 23 10:37:39 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mult8x8 -c mult8x8 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mult8x8 -c mult8x8" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult8x8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mult8x8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mult8x8-struc " "Info: Found design unit 1: mult8x8-struc" {  } { { "mult8x8.vhd" "" { Text "D:/job/mult8x8/mult8x8.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mult8x8 " "Info: Found entity 1: mult8x8" {  } { { "mult8x8.vhd" "" { Text "D:/job/mult8x8/mult8x8.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "andarith.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file andarith.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 andarith-behav " "Info: Found design unit 1: andarith-behav" {  } { { "andarith.vhd" "" { Text "D:/job/mult8x8/andarith.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 andarith " "Info: Found entity 1: andarith" {  } { { "andarith.vhd" "" { Text "D:/job/mult8x8/andarith.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg16b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg16b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg16b-behav " "Info: Found design unit 1: reg16b-behav" {  } { { "reg16b.vhd" "" { Text "D:/job/mult8x8/reg16b.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 reg16b " "Info: Found entity 1: reg16b" {  } { { "reg16b.vhd" "" { Text "D:/job/mult8x8/reg16b.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sreg8b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sreg8b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sreg8b-behav " "Info: Found design unit 1: sreg8b-behav" {  } { { "sreg8b.vhd" "" { Text "D:/job/mult8x8/sreg8b.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sreg8b " "Info: Found entity 1: sreg8b" {  } { { "sreg8b.vhd" "" { Text "D:/job/mult8x8/sreg8b.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "arictl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file arictl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 arictl-behav " "Info: Found design unit 1: arictl-behav" {  } { { "arictl.vhd" "" { Text "D:/job/mult8x8/arictl.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 arictl " "Info: Found entity 1: arictl" {  } { { "arictl.vhd" "" { Text "D:/job/mult8x8/arictl.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_lgoic_vector mult8x8.vhd(32) " "Error (10482): VHDL error at mult8x8.vhd(32): object \"std_lgoic_vector\" is used but not declared" {  } { { "mult8x8.vhd" "" { Text "D:/job/mult8x8/mult8x8.vhd" 32 0 0 } }  } 0 10482 "VHDL error at %2!s!: object \"%1!s!\" is used but not declared" 0 0}
{ "Error" "EVRFX_VHDL_UNIT_INGONRED_ERR" "struc mult8x8.vhd(12) " "Error (10523): Ignored construct struc at mult8x8.vhd(12) due to previous errors" {  } { { "mult8x8.vhd" "" { Text "D:/job/mult8x8/mult8x8.vhd" 12 0 0 } }  } 0 10523 "Ignored construct %1!s! at %2!s! due to previous errors" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Mon Oct 23 10:37:41 2006 " "Error: Processing ended: Mon Oct 23 10:37:41 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}