arictl.vhd

来自「一个用VerilogHDL语言编写的8X8的乘法器」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity arictl is
	port(clk:in std_logic;
	  clkout:out std_logic;
	  ariend:out std_logic
	    );
end arictl;
architecture behav of arictl is
	signal cnt4b:std_logic_vector(3 downto 0);
begin
	rstall<=start;
	process(clk,start)
	begin
		if start='1' then cnt4b<="0000";
			elsif clk 'event and clk='1' then
				if cnt4b<8 then
					cnt4b<=cnt4b+1;
			    end if;
		end if;
	end process;
	process(clk,cnt4b,start)
	begin
	if start='0' then
		if cnt4b<8 then
				clkout<=clk;
				ariend<='0';
			else clkout<='0';
			     ariend<='1';
		end if;
			else clkout<=clk;
			     ariend<='0';
	end if;
	end process;
end behav;