mod6_cnt.v

一个用VerilogHDL语言编写的模6的二进制计数器

module mod6_cnt(
				//input
				clk,
				rst_n,
				//output
				cnt_out,
				);
			input clk;
			input rst_n;
			output[2:0] cnt_out;
			reg[2:0]    cnt_out;
			
			always@(posedge clk or negedge rst_n)
			begin
				if(rst_n==1'b0)
				   cnt_out<=3'b0;
				else if(cnt_out==3'b101)
				   cnt_out<=3'b0;
				else
				   cnt_out<=cnt_out+1;
			end
endmodule