📄 mod6_cnt.tan.rpt
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Timing Analyzer report for mod6_cnt
Thu Nov 02 10:43:59 2006
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
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to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------+-----------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------+-----------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 6.593 ns ; cnt_out[0]~reg0 ; cnt_out[0] ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt_out[1]~reg0 ; cnt_out[2]~reg0 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------+-----------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-----------------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt_out[2]~reg0 ; cnt_out[1]~reg0 ; clk ; clk ; None ; None ; 0.857 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt_out[1]~reg0 ; cnt_out[2]~reg0 ; clk ; clk ; None ; None ; 0.857 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt_out[1]~reg0 ; cnt_out[1]~reg0 ; clk ; clk ; None ; None ; 0.738 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt_out[2]~reg0 ; cnt_out[2]~reg0 ; clk ; clk ; None ; None ; 0.738 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt_out[0]~reg0 ; cnt_out[1]~reg0 ; clk ; clk ; None ; None ; 0.635 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt_out[0]~reg0 ; cnt_out[2]~reg0 ; clk ; clk ; None ; None ; 0.630 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt_out[0]~reg0 ; cnt_out[0]~reg0 ; clk ; clk ; None ; None ; 0.629 ns ;
+-------+------------------------------------------------+-----------------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-----------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-----------------+------------+------------+
; N/A ; None ; 6.593 ns ; cnt_out[0]~reg0 ; cnt_out[0] ; clk ;
; N/A ; None ; 6.366 ns ; cnt_out[1]~reg0 ; cnt_out[1] ; clk ;
; N/A ; None ; 6.200 ns ; cnt_out[2]~reg0 ; cnt_out[2] ; clk ;
+-------+--------------+------------+-----------------+------------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Nov 02 10:43:59 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mod6_cnt -c mod6_cnt --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "cnt_out[2]~reg0" and destination register "cnt_out[1]~reg0"
Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.857 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y30_N1; Fanout = 3; REG Node = 'cnt_out[2]~reg0'
Info: 2: + IC(0.399 ns) + CELL(0.458 ns) = 0.857 ns; Loc. = LC_X52_Y30_N5; Fanout = 3; REG Node = 'cnt_out[1]~reg0'
Info: Total cell delay = 0.458 ns ( 53.44 % )
Info: Total interconnect delay = 0.399 ns ( 46.56 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.872 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X52_Y30_N5; Fanout = 3; REG Node = 'cnt_out[1]~reg0'
Info: Total cell delay = 1.370 ns ( 47.70 % )
Info: Total interconnect delay = 1.502 ns ( 52.30 % )
Info: - Longest clock path from clock "clk" to source register is 2.872 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X52_Y30_N1; Fanout = 3; REG Node = 'cnt_out[2]~reg0'
Info: Total cell delay = 1.370 ns ( 47.70 % )
Info: Total interconnect delay = 1.502 ns ( 52.30 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Micro setup delay of destination is 0.010 ns
Info: tco from clock "clk" to destination pin "cnt_out[0]" through register "cnt_out[0]~reg0" is 6.593 ns
Info: + Longest clock path from clock "clk" to source register is 2.872 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X52_Y30_N2; Fanout = 4; REG Node = 'cnt_out[0]~reg0'
Info: Total cell delay = 1.370 ns ( 47.70 % )
Info: Total interconnect delay = 1.502 ns ( 52.30 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Longest register to pin delay is 3.565 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y30_N2; Fanout = 4; REG Node = 'cnt_out[0]~reg0'
Info: 2: + IC(1.161 ns) + CELL(2.404 ns) = 3.565 ns; Loc. = PIN_B4; Fanout = 0; PIN Node = 'cnt_out[0]'
Info: Total cell delay = 2.404 ns ( 67.43 % )
Info: Total interconnect delay = 1.161 ns ( 32.57 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Thu Nov 02 10:43:59 2006
Info: Elapsed time: 00:00:00
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