mod6_cnt.fit.summary

一个用VerilogHDL语言编写的模6的二进制计数器

Fitter Status : Successful - Thu Nov 02 10:43:49 2006
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : mod6_cnt
Top-level Entity Name : mod6_cnt
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 3 / 10,570 ( < 1 % )
Total pins : 5 / 336 ( 1 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )