usb_new_vsc9_ram_addressor.vhd

实现USB接口功能的VHDL和verilog完整源代码

      port map (a1  => n000023,
                a2  => n000074,
                z   => n000036);

   u000014: an03d1
      port map (a1  => n000074,
                a2  => n000032,
                a3  => n000021,
                z   => n000041);

   u000015_reg: dfntnq1
      port map (d   => n000042,
                cp  => n000001,
                q   => n000011);

   u000016_reg: dfntnq1
      port map (d   => n000041,
                cp  => n000001,
                q   => n000010);

   u000017_reg: dfntnq1
      port map (d   => n000040,
                cp  => n000001,
                q   => n000009);

   u000018_reg: dfntnq1
      port map (d   => n000039,
                cp  => n000001,
                q   => n000008);

   u000019_reg: dfntnq1
      port map (d   => n000038,
                cp  => n000001,
                q   => n000007);

   u000020_reg: dfntnq1
      port map (d   => n000037,
                cp  => n000001,
                q   => n000006);

   u000021_reg: dfntnq1
      port map (d   => n000036,
                cp  => n000001,
                q   => n000005);

   u000022: in01d2
      port map (i   => n000020,
                zn  => n000063);

   u000023: in01d2
      port map (i   => n000004,
                zn  => n000020);

   u000024: mx21d1
      port map (i0  => n000020,
                i1  => n000034,
                s   => n000021,
                z   => n000035);

   u000025: mx21d1
      port map (i0  => n000020,
                i1  => n000030,
                s   => n000021,
                z   => n000031);

   u000026: mx21d1
      port map (i0  => n000020,
                i1  => n000028,
                s   => n000021,
                z   => n000029);

   u000027: mx21d1
      port map (i0  => n000020,
                i1  => n000026,
                s   => n000021,
                z   => n000027);

   u000028: mx21d1
      port map (i0  => n000020,
                i1  => n000024,
                s   => n000021,
                z   => n000025);

   u000029: mx21d1
      port map (i0  => n000020,
                i1  => n000022,
                s   => n000021,
                z   => n000023);

   u000030: mx21d1
      port map (i0  => n000015,
                i1  => n000018,
                s   => n000020,
                z   => n000012);

   u000031: nd02d2
      port map (a1  => n000012,
                a2  => n000003,
                zn  => n000021);

   u000032: nd02d1
      port map (a1  => n000006,
                a2  => n000005,
                zn  => n000014);

   u000033: nd04d1
      port map (a1  => n000011,
                a3  => n000008,
                a4  => n000007,
                a2  => n000009,
                zn  => n000013);

   u000034: ni01d2
      port map (i   => n000002,
                z   => n000074);

   u000035: nr02d1
      port map (a1  => n000014,
                a2  => n000013,
                zn  => n000015);

   u000036: nr03d1
      port map (a1  => n000007,
                a2  => n000006,
                a3  => n000005,
                zn  => n000017);

   u000037: nr04d1
      port map (a1  => n000011,
                a2  => n000010,
                a3  => n000009,
                a4  => n000008,
                zn  => n000016);

   u000038: xn02d1
      port map (a1  => n000010,
                a2  => n000063,
                zn  => n000047);

   u000039: xn02d1
      port map (a1  => n000009,
                a2  => n000063,
                zn  => n000050);

   u000040: xn02d1
      port map (a1  => n000008,
                a2  => n000063,
                zn  => n000053);

   u000041: xn02d1
      port map (a1  => n000007,
                a2  => n000063,
                zn  => n000056);

   u000042: xn02d1
      port map (a1  => n000006,
                a2  => n000063,
                zn  => n000059);

   u000043: xn02d1
      port map (a1  => n000005,
                a2  => n000063,
                zn  => n000062);

   u000044: xo02d1
      port map (a1  => n000011,
                a2  => n000046,
                z   => n000034);

   u000045: xo02d1
      port map (a1  => n000049,
                a2  => n000010,
                z   => n000032);

   u000046: xo02d1
      port map (a1  => n000052,
                a2  => n000009,
                z   => n000030);

   u000047: xo02d1
      port map (a1  => n000055,
                a2  => n000008,
                z   => n000028);

   u000048: xo02d1
      port map (a1  => n000058,
                a2  => n000007,
                z   => n000026);

   u000049: xo02d1
      port map (a1  => n000061,
                a2  => n000006,
                z   => n000024);

   u000050: xo02d1
      port map (a1  => n000003,
                a2  => n000005,
                z   => n000022);


end STRUCTURAL; -- vsc9_ram_addressor

-- -----------------------------------------------------------------------------
-- vsc9_ram_addressor : RTL VHDL
-- (RTL is optimized for simulation, not synthesis)
-- -----------------------------------------------------------------------------


--synopsys translate_off
architecture RTL of vsc9_ram_addressor is

SIGNAL   tcimax : STD_LOGIC;
SIGNAL   tcimin : STD_LOGIC;
SIGNAL     TCIv : STD_LOGIC;
SIGNAL     Qv   : STD_LOGIC_VECTOR(6 downto 0);
CONSTANT  sreset_value : STD_LOGIC_VECTOR(6 downto 0) := "0000000";
CONSTANT  MAXVAL : STD_LOGIC_VECTOR(6 downto 0) := "1011111";
CONSTANT  MINVAL : STD_LOGIC_VECTOR(6 downto 0) := "0000000";

begin


-- -----------------------------------------------------------------------------
   mk_q : process (clk)
-- -----------------------------------------------------------------------------
   begin
     if (clk = '1') and (clk'event) then
       if (csn = '0') then
         Qv <= sreset_value after 1 ns;
       elsif (cen = '1') then
         if (UP = '1') then
           if (((Qv <= MINVAL) or (Qv >= MAXVAL)) and 
                                (HDLi_Reduce_And(Qv or not(MAXVAL)) = '1')) then
             Qv <= MINVAL;
           else
             Qv <= QV+'1';
           end if;
         else
           if (((Qv <= MINVAL) or (Qv >= MAXVAL)) and 
                                (HDLi_Reduce_And(not(Qv) or MINVAL) = '1')) then
             Qv <= MAXVAL;
           else
             Qv <= QV-'1';
           end if;
         end if;
       end if; -- csn or cen or load
     end if; -- if clock'event
   end process;

   tcimax <= '1' when (((Qv <= MINVAL) or (Qv >= MAXVAL)) and 
             (HDLi_Reduce_And(Qv or not(MAXVAL)) = '1')) else '0';
   tcimin <= '1' when (((Qv <= MINVAL) or (Qv >= MAXVAL)) and 
             (HDLi_Reduce_And(not(Qv) or MINVAL) = '1')) else '0';
   TCIv <= tcimax when (UP = '1') else tcimin;

   TCI <= TCIv;

   Q <= Qv;

end RTL; -- vsc9_ram_addressor

--synopsys translate_on
-- -----------------------------------------------------------------------------
-- VHDL Component Instantiation:
-- -----------------------------------------------------------------------------
-- component vsc9_ram_addressor
--    port ( clk    : in STD_LOGIC;
--           csn    : in STD_LOGIC;
--           cen    : in STD_LOGIC;
--           up     : in STD_LOGIC;
--           q      : out STD_LOGIC_VECTOR(6 downto 0);
--           tci    : out STD_LOGIC);
-- end component;

--
-- u1: vsc9_ram_addressor
--    port map ( clk    => ,      -- Clock Input
--               csn    => ,      -- Clear Synchronous Not Input
--               cen    => ,      -- Count Enable Input
--               up     => ,      -- Direction Control Input
--               q      => ,      --  7 bit Result
--               tci    => );     -- Terminal Count Indicator
-- -----------------------------------------------------------------------------
-- VHDL Synthesis Commands:
-- -----------------------------------------------------------------------------
--   set_dont_touch find(design, vsc9_ram_addressor, -hierarchy)
--   remove_attribute find(design, vsc9_ram_addressor, -hierarchy) dont_touch
--   set_ungroup find(design, vsc9_ram_addressor, -hierarchy)
-- -----------------------------------------------------------------------------