usb_new_pck_general.vhdl

实现USB接口功能的VHDL和verilog完整源代码

  end conv_active_low;

  function conv_active_high (Arg: booleans)
           return unsigned is
    variable Result: unsigned(Arg'range);
  begin
    for i in Result'range loop
      Result(i) := conv_active_high(Arg(i));
    end loop;
    return Result;
  end conv_active_high;

  function conv_active_low (Arg: unsigned)
           return booleans is
    variable Result: booleans(Arg'range);
  begin
    for i in Result'range loop
      Result(i) := conv_active_low(Arg(i));
    end loop;
    return Result;
  end conv_active_low;

  function conv_active_high (Arg: unsigned)
           return booleans is
    variable Result: booleans(Arg'range);
  begin
    for i in Result'range loop
      Result(i) := conv_active_high(Arg(i));
    end loop;
    return Result;
  end conv_active_high;

  -- overload to_integer for std_logic
  function to_integer (Arg: std_logic)
           return integer is
  begin
    if Arg='1' or Arg='H' then
      Return 1;
    elsif Arg='0' or Arg='L' then
      return 0;
    else
      assert FALSE
      report "to_integer(std_logic): argument is not 0, 1, H or L. Returning 0" severity WARNING;
      return 0;
    end if;
  end to_integer;                               



  -- overload shl (shift left) and shr (shift right) from Synopsys'
  -- arithmetic package, so that the shift value can be a natural

  function shl(Arg: unsigned; count: natural) return unsigned is
    subtype rtype is unsigned ((Arg'length-1) downto 0);
    variable Result: rtype;
  begin
    Result := Arg; 
    if (count > 0) then
      if (Arg'length = 1) then
        Result := "0";
      else 
        for i in 1 to Arg'length loop
          if (count >= i) then
            Result := Result((Arg'length-2) downto 0) & "0"; 
          else
            exit;
          end if;
        end loop;
      end if;
    end if;
    return Result;
  end;

  function shr(Arg: unsigned; count: natural) return unsigned is
    subtype rtype is unsigned ((Arg'length-1) downto 0);
    variable Result: rtype;
  begin
    Result := Arg; 
    if (count > 0) then
      if (Arg'length = 1) then
        Result := "0";
      else 
        for i in 1 to Arg'length loop
          if (count >= i) then
            Result := "0" & Result((Arg'length-1) downto 1); 
          else
            exit;
          end if;
        end loop;
      end if;
    end if;
    return Result;
  end;

  -- reduce functions 

  function and_reduce(Arg: unsigned) return one_bit is
    variable Result: one_bit;
  begin
    Result := '1';
    for i in Arg'range loop
      Result := Result and Arg(i);
    end loop;
    return Result;
  end;

  function nand_reduce(Arg: unsigned) return one_bit is
  begin
    return not and_reduce(Arg);
  end;

  function or_reduce(Arg: unsigned) return one_bit is
    variable Result: one_bit;
  begin
    Result := '0';
    for i in Arg'range loop
      Result := Result or Arg(i);
    end loop;
    return Result;
  end;

  function nor_reduce(Arg: unsigned) return one_bit is
  begin
    return not or_reduce(Arg);
  end;

  function xor_reduce(Arg: unsigned) return one_bit is
    variable Result: one_bit;
  begin
    Result := '0';
    for i in Arg'range loop
      Result := Result xor Arg(i);
    end loop;
    return Result;
  end;

  function xnor_reduce(Arg: unsigned) return one_bit is
  begin
    return not xor_reduce(Arg);
  end;

  function and_reduce(Arg: booleans) return boolean is
    variable Result: boolean;
  begin
    Result := TRUE;
    for i in Arg'range loop
      Result := Result and Arg(i);
    end loop;
    return Result;
  end;

  function nand_reduce(Arg: booleans) return boolean is
  begin
    return not and_reduce(Arg);
  end;

  function or_reduce(Arg: booleans) return boolean is
    variable Result: boolean;
  begin
    Result := FALSE;
    for i in Arg'range loop
      Result := Result or Arg(i);
    end loop;
    return Result;
  end;

  function nor_reduce(Arg: booleans) return boolean is
  begin
    return not or_reduce(Arg);
  end;

  function xor_reduce(Arg: booleans) return boolean is
    variable Result: boolean;
  begin
    Result := FALSE;
    for i in Arg'range loop
      Result := Result xor Arg(i);
    end loop;
    return Result;
  end;

  function xnor_reduce(Arg: booleans) return boolean is
  begin
    return not xor_reduce(Arg);
  end;

  -- The following functions were defined in arithmetic in version2.2b
  -- but where no longer defined in std_logic_arith package
  -- therefore...
  -- redundant qualifying when making Result
  -- is necessary because of synthesis bug

--  function "and" (L, R: unsigned) return unsigned is
--    variable Result: std_logic_vector(L'range);
--  begin
--    Result := std_logic_vector(unsigned'(L)) and
--              std_logic_vector(unsigned'(R));
--    return unsigned(Result);
--  end;
  
-- function "nand" (L, R: unsigned) return unsigned is
--   variable Result: std_logic_vector(L'range);
-- begin
--   Result := std_logic_vector(unsigned'(L)) nand
--             std_logic_vector(unsigned'(R));
--   return unsigned(Result);
-- end;

-- function "or" (L, R: unsigned) return unsigned is
--   variable Result: std_logic_vector(L'range);
-- begin
--   Result := std_logic_vector(unsigned'(L)) or
--             std_logic_vector(unsigned'(R));
--   return unsigned(Result);
-- end;

-- function "nor" (L, R: unsigned) return unsigned is
--   variable Result: std_logic_vector(L'range);
-- begin
--   Result := std_logic_vector(unsigned'(L)) nor
--             std_logic_vector(unsigned'(R));
--   return unsigned(Result);
-- end;

-- function "xor" (L, R: unsigned) return unsigned is
--   variable Result: std_logic_vector(L'range);
-- begin
--   Result := std_logic_vector(unsigned'(L)) xor
--             std_logic_vector(unsigned'(R));
--   return unsigned(Result);
-- end;

--  function xnor (L, R: unsigned) return unsigned is
--    variable Result: std_logic_vector(L'range);
--  begin
--    Result := (not (std_logic_vector(unsigned'(L)) xor
--		    std_logic_vector(unsigned'(R))));
--    return unsigned(Result);
--  end;

-- function "not" (L: unsigned) return unsigned is
--   variable Result: std_logic_vector(L'range);
-- begin
--   Result := not std_logic_vector(unsigned'(L));
--   return unsigned(Result);
-- end;

-- function "and" (L, R: signed) return signed is
--   variable Result: std_logic_vector(L'range);
-- begin
--   Result := std_logic_vector(signed'(L)) and
--             std_logic_vector(signed'(R));
--   return signed(Result);
-- end;

-- function "nand" (L, R: signed) return signed is
--   variable Result: std_logic_vector(L'range);
-- begin
--   Result := std_logic_vector(signed'(L)) nand
--             std_logic_vector(signed'(R));
--   return signed(Result);
-- end;

-- function "or" (L, R: signed) return signed is
--   variable Result: std_logic_vector(L'range);
-- begin
--   Result := std_logic_vector(signed'(L)) or
--             std_logic_vector(signed'(R));
--   return signed(Result);
-- end;

-- function "nor" (L, R: signed) return signed is
--   variable Result: std_logic_vector(L'range);
-- begin
--   Result := std_logic_vector(signed'(L)) nor
--             std_logic_vector(signed'(R));
--   return signed(Result);
-- end;

-- function "xor" (L, R: signed) return signed is
--   variable Result: std_logic_vector(L'range);
-- begin
--   Result := std_logic_vector(signed'(L)) xor
--             std_logic_vector(signed'(R));
--   return signed(Result);
-- end;

--  function xnor (L, R: signed) return signed is
--    variable Result: std_logic_vector(L'range);
--  begin
--    Result := (not (std_logic_vector(signed'(L)) xor
--                    std_logic_vector(signed'(R))));
--    return signed(Result);
--  end;

-- function "not" (L: signed) return signed is
--   variable Result: std_logic_vector(L'range);
-- begin
--   Result := not std_logic_vector(signed'(L));
--   return signed(Result);
-- end;
--

  -- functions to reverse (mirror) an array of bits  

  function Reverse(Arg: signed) return signed is
    variable Result: signed(Arg'reverse_range);
  begin
    for i in Arg'range loop
      Result(i) := Arg(i);
    end loop;
    return Result;
  end Reverse;

  function Reverse(Arg: unsigned) return unsigned is
    variable Result: unsigned(Arg'reverse_range);
  begin
    for i in Arg'range loop
      Result(i) := Arg(i);
    end loop;
    return Result;
  end Reverse;

  -- functions to generate/check odd/even parity

  function GenerateOddParity (Arg: unsigned)
	   return one_bit is
    variable Result: one_bit;
  begin
    Result := '1';
    for i in Arg'range loop
      Result := Result xor Arg(i);
    end loop;
    return Result;
  end GenerateOddParity;

  function GenerateEvenParity (Arg: unsigned)
	   return one_bit is
    variable Result: one_bit;
  begin
    Result := '0';
    for i in Arg'range loop
      Result := Result xor Arg(i);
    end loop;
    return Result;
  end GenerateEvenParity;

  function CheckOddParity (Arg: unsigned)
	   return boolean is
    variable Result: boolean;
  begin
    Result := FALSE;
    for i in Arg'range loop
      Result := Result xor (Arg(i) = '1');
    end loop;
    return Result;
  end CheckOddParity;

  function CheckEvenParity (Arg: unsigned)
	   return boolean is
    variable Result: boolean;
  begin
    Result := TRUE;
    for i in Arg'range loop
      Result := Result xor (Arg(i) = '1');
    end loop;
    return Result;
  end CheckEvenParity;

end PCK_GENERAL;