de_mux.map.rpt

一个用VerilogHDL语言编写的多路解复用器

+---------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                        ;
+----------------------------------+-----------------+------------------------+---------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path    ;
+----------------------------------+-----------------+------------------------+---------------------------------+
; de_mux.v                         ; yes             ; User Verilog HDL File  ; D:/job/practice/de_mux/de_mux.v ;
+----------------------------------+-----------------+------------------------+---------------------------------+


+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary          ;
+---------------------------------------------+--------+
; Resource                                    ; Usage  ;
+---------------------------------------------+--------+
; Total logic elements                        ; 8      ;
;     -- Combinational with no register       ; 8      ;
;     -- Register only                        ; 0      ;
;     -- Combinational with a register        ; 0      ;
;                                             ;        ;
; Logic element usage by number of LUT inputs ;        ;
;     -- 4 input functions                    ; 0      ;
;     -- 3 input functions                    ; 4      ;
;     -- 2 input functions                    ; 4      ;
;     -- 1 input functions                    ; 0      ;
;     -- 0 input functions                    ; 0      ;
;         -- Combinational cells for routing  ; 0      ;
;                                             ;        ;
; Logic elements by mode                      ;        ;
;     -- normal mode                          ; 8      ;
;     -- arithmetic mode                      ; 0      ;
;     -- qfbk mode                            ; 0      ;
;     -- register cascade mode                ; 0      ;
;     -- synchronous clear/load mode          ; 0      ;
;     -- asynchronous clear/load mode         ; 0      ;
;                                             ;        ;
; Total registers                             ; 0      ;
; I/O pins                                    ; 8      ;
; Maximum fan-out node                        ; din[0] ;
; Maximum fan-out                             ; 4      ;
; Total fan-out                               ; 24     ;
; Average fan-out                             ; 1.50   ;
+---------------------------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |de_mux                    ; 8 (8)       ; 0            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 8    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |de_mux             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; dout[0]$latch                                      ; Decoder0            ; yes                    ;
; dout[1]$latch                                      ; Decoder0            ; yes                    ;
; dout[2]$latch                                      ; Decoder0            ; yes                    ;
; dout[3]$latch                                      ; Decoder0            ; yes                    ;
; Number of user-specified and inferred latches = 4  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Nov 02 10:37:57 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off de_mux -c de_mux
Info: Found 1 design units, including 1 entities, in source file de_mux.v
    Info: Found entity 1: de_mux
Info: Elaborating entity "de_mux" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at de_mux.v(16): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at de_mux.v(17): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at de_mux.v(18): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at de_mux.v(19): truncated value with size 2 to match size of target (1)
Warning (10240): Verilog HDL Always Construct warning at de_mux.v(13): inferring latch(es) for variable "dout", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at de_mux.v(15): inferred latch for "dout[3]"
Info (10041): Verilog HDL or VHDL info at de_mux.v(15): inferred latch for "dout[2]"
Info (10041): Verilog HDL or VHDL info at de_mux.v(15): inferred latch for "dout[1]"
Info (10041): Verilog HDL or VHDL info at de_mux.v(15): inferred latch for "dout[0]"
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "din[1]"
Info: Implemented 16 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 4 output pins
    Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Processing ended: Thu Nov 02 10:37:58 2006
    Info: Elapsed time: 00:00:02