top.tan.rpt

这是使用VHDL编写的交通灯程序,供大家交流学习

; N/A   ; None         ; 8.595 ns   ; tim4~11       ; time4[0] ; clk        ;
; N/A   ; None         ; 8.535 ns   ; tim4~18       ; time4[0] ; clk        ;
; N/A   ; None         ; 8.530 ns   ; tim3[1]       ; time3[1] ; clk        ;
; N/A   ; None         ; 8.476 ns   ; tim1~9        ; time1[2] ; clk        ;
; N/A   ; None         ; 8.475 ns   ; pre_state1.s0 ; redA     ; clk        ;
; N/A   ; None         ; 8.328 ns   ; tim4~16       ; time4[2] ; clk        ;
; N/A   ; None         ; 8.317 ns   ; tim2~9        ; time2[2] ; clk        ;
; N/A   ; None         ; 8.280 ns   ; tim2~8        ; time2[3] ; clk        ;
; N/A   ; None         ; 8.101 ns   ; pre_state1.s2 ; yellowA  ; clk        ;
; N/A   ; None         ; 8.068 ns   ; tim4~10       ; time4[1] ; clk        ;
; N/A   ; None         ; 8.063 ns   ; pre_state1.s1 ; greenA   ; clk        ;
; N/A   ; None         ; 8.061 ns   ; tim4~9        ; time4[2] ; clk        ;
; N/A   ; None         ; 8.058 ns   ; tim2[2]       ; time2[2] ; clk        ;
; N/A   ; None         ; 8.053 ns   ; tim1~11       ; time1[0] ; clk        ;
; N/A   ; None         ; 8.039 ns   ; pre_state2.s0 ; yellowB  ; clk        ;
; N/A   ; None         ; 7.740 ns   ; tim3~11       ; time3[0] ; clk        ;
; N/A   ; None         ; 7.739 ns   ; tim3~9        ; time3[2] ; clk        ;
; N/A   ; None         ; 7.710 ns   ; tim1~0        ; time1[3] ; clk        ;
; N/A   ; None         ; 7.708 ns   ; pre_state2.s2 ; greenB   ; clk        ;
; N/A   ; None         ; 7.664 ns   ; tim3~0        ; time3[3] ; clk        ;
; N/A   ; None         ; 7.654 ns   ; tim2~10       ; time2[1] ; clk        ;
; N/A   ; None         ; 7.646 ns   ; pre_state2.s1 ; redB     ; clk        ;
+-------+--------------+------------+---------------+----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Aug 16 14:44:54 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off top -c top --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 188.01 MHz between source register "pre_state2.s0" and destination register "next_state2_95" (period= 5.319 ns)
    Info: + Longest register to register delay is 5.058 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y9_N1; Fanout = 7; REG Node = 'pre_state2.s0'
        Info: 2: + IC(0.856 ns) + CELL(0.590 ns) = 1.446 ns; Loc. = LC_X8_Y9_N6; Fanout = 5; COMB Node = 'Select~290'
        Info: 3: + IC(0.430 ns) + CELL(0.590 ns) = 2.466 ns; Loc. = LC_X8_Y9_N8; Fanout = 8; COMB Node = 'reduce_nor~3'
        Info: 4: + IC(0.405 ns) + CELL(0.442 ns) = 3.313 ns; Loc. = LC_X8_Y9_N9; Fanout = 11; COMB Node = 'p2~0'
        Info: 5: + IC(1.138 ns) + CELL(0.607 ns) = 5.058 ns; Loc. = LC_X6_Y9_N4; Fanout = 4; REG Node = 'next_state2_95'
        Info: Total cell delay = 2.229 ns ( 44.07 % )
        Info: Total interconnect delay = 2.829 ns ( 55.93 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.170 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 44; CLK Node = 'clk'
            Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X6_Y9_N4; Fanout = 4; REG Node = 'next_state2_95'
            Info: Total cell delay = 2.180 ns ( 68.77 % )
            Info: Total interconnect delay = 0.990 ns ( 31.23 % )
        Info: - Longest clock path from clock "clk" to source register is 3.170 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 44; CLK Node = 'clk'
            Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X7_Y9_N1; Fanout = 7; REG Node = 'pre_state2.s0'
            Info: Total cell delay = 2.180 ns ( 68.77 % )
            Info: Total interconnect delay = 0.990 ns ( 31.23 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "time2[0]" through register "tim2[0]" is 10.137 ns
    Info: + Longest clock path from clock "clk" to source register is 3.111 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 44; CLK Node = 'clk'
        Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X31_Y10_N6; Fanout = 2; REG Node = 'tim2[0]'
        Info: Total cell delay = 2.180 ns ( 70.07 % )
        Info: Total interconnect delay = 0.931 ns ( 29.93 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.802 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y10_N6; Fanout = 2; REG Node = 'tim2[0]'
        Info: 2: + IC(0.785 ns) + CELL(0.590 ns) = 1.375 ns; Loc. = LC_X30_Y10_N6; Fanout = 6; COMB Node = 'Select~285'
        Info: 3: + IC(3.319 ns) + CELL(2.108 ns) = 6.802 ns; Loc. = PIN_104; Fanout = 0; PIN Node = 'time2[0]'
        Info: Total cell delay = 2.698 ns ( 39.66 % )
        Info: Total interconnect delay = 4.104 ns ( 60.34 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Aug 16 14:44:55 2006
    Info: Elapsed time: 00:00:01