top.tan.qmsg

这是使用VHDL编写的交通灯程序,供大家交流学习

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register pre_state2.s0 register next_state2_95 188.01 MHz 5.319 ns Internal " "Info: Clock \"clk\" has Internal fmax of 188.01 MHz between source register \"pre_state2.s0\" and destination register \"next_state2_95\" (period= 5.319 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.058 ns + Longest register register " "Info: + Longest register to register delay is 5.058 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pre_state2.s0 1 REG LC_X7_Y9_N1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y9_N1; Fanout = 7; REG Node = 'pre_state2.s0'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "" { pre_state2.s0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.590 ns) 1.446 ns Select~290 2 COMB LC_X8_Y9_N6 5 " "Info: 2: + IC(0.856 ns) + CELL(0.590 ns) = 1.446 ns; Loc. = LC_X8_Y9_N6; Fanout = 5; COMB Node = 'Select~290'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "1.446 ns" { pre_state2.s0 Select~290 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.590 ns) 2.466 ns reduce_nor~3 3 COMB LC_X8_Y9_N8 8 " "Info: 3: + IC(0.430 ns) + CELL(0.590 ns) = 2.466 ns; Loc. = LC_X8_Y9_N8; Fanout = 8; COMB Node = 'reduce_nor~3'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "1.020 ns" { Select~290 reduce_nor~3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.405 ns) + CELL(0.442 ns) 3.313 ns p2~0 4 COMB LC_X8_Y9_N9 11 " "Info: 4: + IC(0.405 ns) + CELL(0.442 ns) = 3.313 ns; Loc. = LC_X8_Y9_N9; Fanout = 11; COMB Node = 'p2~0'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "0.847 ns" { reduce_nor~3 p2~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.138 ns) + CELL(0.607 ns) 5.058 ns next_state2_95 5 REG LC_X6_Y9_N4 4 " "Info: 5: + IC(1.138 ns) + CELL(0.607 ns) = 5.058 ns; Loc. = LC_X6_Y9_N4; Fanout = 4; REG Node = 'next_state2_95'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "1.745 ns" { p2~0 next_state2_95 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 114 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.229 ns 44.07 % " "Info: Total cell delay = 2.229 ns ( 44.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.829 ns 55.93 % " "Info: Total interconnect delay = 2.829 ns ( 55.93 % )" {  } {  } 0}  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "5.058 ns" { pre_state2.s0 Select~290 reduce_nor~3 p2~0 next_state2_95 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.058 ns" { pre_state2.s0 Select~290 reduce_nor~3 p2~0 next_state2_95 } { 0.000ns 0.856ns 0.430ns 0.405ns 1.138ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.170 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 44 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 44; CLK Node = 'clk'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "" { clk } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns next_state2_95 2 REG LC_X6_Y9_N4 4 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X6_Y9_N4; Fanout = 4; REG Node = 'next_state2_95'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "1.701 ns" { clk next_state2_95 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 114 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.77 % " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns 31.23 % " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0}  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "3.170 ns" { clk next_state2_95 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 next_state2_95 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.170 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 44 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 44; CLK Node = 'clk'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "" { clk } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns pre_state2.s0 2 REG LC_X7_Y9_N1 7 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X7_Y9_N1; Fanout = 7; REG Node = 'pre_state2.s0'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "1.701 ns" { clk pre_state2.s0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.77 % " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns 31.23 % " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0}  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "3.170 ns" { clk pre_state2.s0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 pre_state2.s0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "3.170 ns" { clk next_state2_95 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 next_state2_95 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "3.170 ns" { clk pre_state2.s0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 pre_state2.s0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 114 -1 0 } }  } 0}  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "5.058 ns" { pre_state2.s0 Select~290 reduce_nor~3 p2~0 next_state2_95 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.058 ns" { pre_state2.s0 Select~290 reduce_nor~3 p2~0 next_state2_95 } { 0.000ns 0.856ns 0.430ns 0.405ns 1.138ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.607ns } } } { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "3.170 ns" { clk next_state2_95 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 next_state2_95 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "3.170 ns" { clk pre_state2.s0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 pre_state2.s0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk time2\[0\] tim2\[0\] 10.137 ns register " "Info: tco from clock \"clk\" to destination pin \"time2\[0\]\" through register \"tim2\[0\]\" is 10.137 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.111 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 44 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 44; CLK Node = 'clk'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "" { clk } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns tim2\[0\] 2 REG LC_X31_Y10_N6 2 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X31_Y10_N6; Fanout = 2; REG Node = 'tim2\[0\]'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "1.642 ns" { clk tim2[0] } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 70.07 % " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns 29.93 % " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0}  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "3.111 ns" { clk tim2[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.111 ns" { clk clk~out0 tim2[0] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.802 ns + Longest register pin " "Info: + Longest register to pin delay is 6.802 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tim2\[0\] 1 REG LC_X31_Y10_N6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y10_N6; Fanout = 2; REG Node = 'tim2\[0\]'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "" { tim2[0] } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.785 ns) + CELL(0.590 ns) 1.375 ns Select~285 2 COMB LC_X30_Y10_N6 6 " "Info: 2: + IC(0.785 ns) + CELL(0.590 ns) = 1.375 ns; Loc. = LC_X30_Y10_N6; Fanout = 6; COMB Node = 'Select~285'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "1.375 ns" { tim2[0] Select~285 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.319 ns) + CELL(2.108 ns) 6.802 ns time2\[0\] 3 PIN PIN_104 0 " "Info: 3: + IC(3.319 ns) + CELL(2.108 ns) = 6.802 ns; Loc. = PIN_104; Fanout = 0; PIN Node = 'time2\[0\]'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "5.427 ns" { Select~285 time2[0] } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.698 ns 39.66 % " "Info: Total cell delay = 2.698 ns ( 39.66 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.104 ns 60.34 % " "Info: Total interconnect delay = 4.104 ns ( 60.34 % )" {  } {  } 0}  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "6.802 ns" { tim2[0] Select~285 time2[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.802 ns" { tim2[0] Select~285 time2[0] } { 0.000ns 0.785ns 3.319ns } { 0.000ns 0.590ns 2.108ns } } }  } 0}  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "3.111 ns" { clk tim2[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.111 ns" { clk clk~out0 tim2[0] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "6.802 ns" { tim2[0] Select~285 time2[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.802 ns" { tim2[0] Select~285 time2[0] } { 0.000ns 0.785ns 3.319ns } { 0.000ns 0.590ns 2.108ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 16 14:44:55 2006 " "Info: Processing ended: Wed Aug 16 14:44:55 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}