top.map.qmsg

这是使用VHDL编写的交通灯程序,供大家交流学习

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 16 14:44:34 2006 " "Info: Processing started: Wed Aug 16 14:44:34 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top -c top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "controller.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 controller-arch " "Info: Found design unit 1: controller-arch" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 controller " "Info: Found entity 1: controller" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "controller " "Info: Elaborating entity \"controller\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "tim1~12 tim1~0 " "Info: Duplicate register \"tim1~12\" merged to single register \"tim1~0\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim1\[3\] tim1~0 " "Info: Duplicate register \"tim1\[3\]\" merged to single register \"tim1~0\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim1~14 tim1~9 " "Info: Duplicate register \"tim1~14\" merged to single register \"tim1~9\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim1\[2\] tim1~9 " "Info: Duplicate register \"tim1\[2\]\" merged to single register \"tim1~9\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim1\[1\] tim1~10 " "Info: Duplicate register \"tim1\[1\]\" merged to single register \"tim1~10\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim1~16 tim1~11 " "Info: Duplicate register \"tim1~16\" merged to single register \"tim1~11\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim1\[0\] tim1~11 " "Info: Duplicate register \"tim1\[0\]\" merged to single register \"tim1~11\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim2~12 tim2~8 " "Info: Duplicate register \"tim2~12\" merged to single register \"tim2~8\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim2~13 tim2~9 " "Info: Duplicate register \"tim2~13\" merged to single register \"tim2~9\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim2~14 tim2~10 " "Info: Duplicate register \"tim2~14\" merged to single register \"tim2~10\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim2\[1\] tim2~10 " "Info: Duplicate register \"tim2\[1\]\" merged to single register \"tim2~10\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim2~15 tim2~11 " "Info: Duplicate register \"tim2~15\" merged to single register \"tim2~11\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim3~12 tim3~0 " "Info: Duplicate register \"tim3~12\" merged to single register \"tim3~0\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim3\[3\] tim3~0 " "Info: Duplicate register \"tim3\[3\]\" merged to single register \"tim3~0\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim3~13 tim3~9 " "Info: Duplicate register \"tim3~13\" merged to single register \"tim3~9\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim3\[2\] tim3~9 " "Info: Duplicate register \"tim3\[2\]\" merged to single register \"tim3~9\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim3~14 tim3~10 " "Info: Duplicate register \"tim3~14\" merged to single register \"tim3~10\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim3~15 tim3~11 " "Info: Duplicate register \"tim3~15\" merged to single register \"tim3~11\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim3\[0\] tim3~11 " "Info: Duplicate register \"tim3\[0\]\" merged to single register \"tim3~11\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim4~17 tim4~10 " "Info: Duplicate register \"tim4~17\" merged to single register \"tim4~10\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim4\[1\] tim4~10 " "Info: Duplicate register \"tim4\[1\]\" merged to single register \"tim4~10\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim4\[3\] tim4~15 " "Info: Duplicate register \"tim4\[3\]\" merged to single register \"tim4~15\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim4\[2\] tim4~16 " "Info: Duplicate register \"tim4\[2\]\" merged to single register \"tim4~16\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tim4\[0\] tim4~18 " "Info: Duplicate register \"tim4\[0\]\" merged to single register \"tim4~18\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 14 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|controller\|pre_state1 3 0 " "Info: State machine \"\|controller\|pre_state1\" contains 3 states and 0 state bits" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 13 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|controller\|pre_state2 3 0 " "Info: State machine \"\|controller\|pre_state2\" contains 3 states and 0 state bits" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 13 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|controller\|fsm19 3 0 " "Info: State machine \"\|controller\|fsm19\" contains 3 states and 0 state bits" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 13 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|controller\|fsm48 3 0 " "Info: State machine \"\|controller\|fsm48\" contains 3 states and 0 state bits" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 13 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|controller\|next_state1 3 0 " "Info: State machine \"\|controller\|next_state1\" contains 3 states and 0 state bits" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 13 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|controller\|fsm71 3 0 " "Info: State machine \"\|controller\|fsm71\" contains 3 states and 0 state bits" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 13 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|controller\|fsm94 3 0 " "Info: State machine \"\|controller\|fsm94\" contains 3 states and 0 state bits" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 13 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|controller\|next_state2 3 0 " "Info: State machine \"\|controller\|next_state2\" contains 3 states and 0 state bits" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 13 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|controller\|pre_state1 " "Info: Selected Auto state machine encoding method for state machine \"\|controller\|pre_state1\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 13 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|controller\|pre_state1 " "Info: Encoding result for state machine \"\|controller\|pre_state1\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pre_state1.s2 " "Info: Encoded state bit \"pre_state1.s2\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pre_state1.s1 " "Info: Encoded state bit \"pre_state1.s1\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pre_state1.s0 " "Info: Encoded state bit \"pre_state1.s0\"" {  } {  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|controller\|pre_state1.s0 000 " "Info: State \"\|controller\|pre_state1.s0\" uses code string \"000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|controller\|pre_state1.s1 011 " "Info: State \"\|controller\|pre_state1.s1\" uses code string \"011\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|controller\|pre_state1.s2 101 " "Info: State \"\|controller\|pre_state1.s2\" uses code string \"101\"" {  } {  } 0}  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 13 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|controller\|pre_state2 " "Info: Selected Auto state machine encoding method for state machine \"\|controller\|pre_state2\"" {  } { { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 13 -1 0 } }  } 0}