top.fit.qmsg

这是使用VHDL编写的交通灯程序,供大家交流学习

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "22 unused 3.30 0 22 0 " "Info: Number of I/O pins in group: 22 (unused VREF, 3.30 VCCIO, 0 input, 22 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 4 40 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  40 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 42 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 45 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 42 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.835 ns register register " "Info: Estimated most critical path is register to register delay of 3.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pre_state2.s0 1 REG LAB_X7_Y9 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y9; Fanout = 7; REG Node = 'pre_state2.s0'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "" { pre_state2.s0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.903 ns) + CELL(0.114 ns) 1.017 ns Select~290 2 COMB LAB_X8_Y9 5 " "Info: 2: + IC(0.903 ns) + CELL(0.114 ns) = 1.017 ns; Loc. = LAB_X8_Y9; Fanout = 5; COMB Node = 'Select~290'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "1.017 ns" { pre_state2.s0 Select~290 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.292 ns) 1.681 ns reduce_nor~3 3 COMB LAB_X8_Y9 8 " "Info: 3: + IC(0.372 ns) + CELL(0.292 ns) = 1.681 ns; Loc. = LAB_X8_Y9; Fanout = 8; COMB Node = 'reduce_nor~3'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "0.664 ns" { Select~290 reduce_nor~3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.292 ns) 2.345 ns p2~0 4 COMB LAB_X8_Y9 11 " "Info: 4: + IC(0.372 ns) + CELL(0.292 ns) = 2.345 ns; Loc. = LAB_X8_Y9; Fanout = 11; COMB Node = 'p2~0'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "0.664 ns" { reduce_nor~3 p2~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.181 ns) + CELL(0.309 ns) 3.835 ns next_state2_72 5 REG LAB_X6_Y9 3 " "Info: 5: + IC(1.181 ns) + CELL(0.309 ns) = 3.835 ns; Loc. = LAB_X6_Y9; Fanout = 3; REG Node = 'next_state2_72'" {  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "1.490 ns" { p2~0 next_state2_72 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/traffic_controller/controller.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.007 ns 26.26 % " "Info: Total cell delay = 1.007 ns ( 26.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.828 ns 73.74 % " "Info: Total interconnect delay = 2.828 ns ( 73.74 % )" {  } {  } 0}  } { { "E:/traffic_controller/db/top_cmp.qrpt" "" { Report "E:/traffic_controller/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "E:/traffic_controller/db/top.quartus_db" { Floorplan "E:/traffic_controller/" "" "3.835 ns" { pre_state2.s0 Select~290 reduce_nor~3 p2~0 next_state2_72 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 16 14:44:48 2006 " "Info: Processing ended: Wed Aug 16 14:44:48 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}