controller.vhd

这是使用VHDL编写的交通灯程序,供大家交流学习

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity controller is
port(clk,reset: in std_logic;
     --flash: out std_logic;
     time1,time2,time3,time4: out std_logic_vector(3 downto 0);
     redA,greenA,yellowA,redB,greenB,yellowB: out std_logic);
end entity;
architecture arch of controller is 
type state is (s0,s1,s2);
signal pre_state1,next_state1,pre_state2,next_state2: state;
signal tim1,tim2,tim3,tim4: std_logic_vector(3 downto 0);
begin
p0:process(clk,reset)
begin
if reset='1' then
  --tim1<="0010";
  --tim2<="1001";
  pre_state1<=s0;
  pre_state2<=s0;
  --tim3<="0010";
  --tim4<="0100";
elsif(clk'event and clk='1') then
  pre_state1<=next_state1;
  pre_state2<=next_state2;
end if;
end process;
p1:process(clk,pre_state1,next_state1)
begin
case pre_state1 is
   when s0 =>
          redA<='1';--红灯
          greenA<='0';
          yellowA<='0';
          if(clk'event and clk='1') then
             if(tim1="0000" and tim2="0000") then
                tim1<="0010";
                tim2<="0100";
                next_state1<=s1;
             elsif(tim2="0000") then
                tim1<=tim1-1;
                tim2<="1001";
                next_state1<=s0;
             else
                tim2<=tim2-1;
                next_state1<=s0;
             end if;
          end if;
   when s1 =>
          redA<='0';--绿灯
          greenA<='1';
          yellowA<='0';
          if(clk'event and clk='1') then
             if(tim1="0000" and tim2="0000") then
                tim1<="0000";
                tim2<="0100";
                next_state1<=s2;
             elsif(tim2="0000") then
                tim1<=tim1-1;
                tim2<="1001";
                next_state1<=s1;
             else
                tim2<=tim2-1;
                next_state1<=s1;
             end if;
          end if;
   when s2 =>
          redA<='0';--黄灯
          greenA<='0';
          yellowA<='1';
          if(clk'event and clk='1') then
             if(tim1="0000" and tim2="0000") then
                tim1<="0010";
                tim2<="1001";
                next_state1<=s0;
             elsif(tim2="0000") then
                tim1<=tim1-1;
                tim2<="1001";
                next_state1<=s2;
             else
                tim2<=tim2-1;
                next_state1<=s2;
             end if;
          end if;
end case;
end process;
p2:process(clk,pre_state2,next_state2)
begin
case pre_state2 is
   when s0 =>
          redB<='0';--黄灯
          greenB<='0';
          yellowB<='1';
          if(clk'event and clk='1') then
             if(tim3="0000" and tim4="0000") then
                tim3<="0010";
                tim4<="1001";
                next_state2<=s1;
             elsif(tim4="0000") then
                tim3<=tim3-1;
                tim4<="1001";
                next_state2<=s0;
             else
                tim4<=tim4-1;
                next_state2<=s0;
             end if;
          end if;
   when s1 =>
          redB<='1';--红灯
          greenB<='0';
          yellowB<='0';
          if(clk'event and clk='1') then
             if(tim3="0000" and tim4="0000") then
                tim3<="0010";
                tim4<="0100";
                next_state2<=s2;
             elsif(tim4="0000") then
                tim3<=tim3-1;
                tim4<="1001";
                next_state2<=s1;
             else
                tim4<=tim4-1;
                next_state2<=s1;
             end if;
          end if;
   when s2 =>
          redB<='0';--绿灯
          greenB<='1';
          yellowB<='0';
          if(clk'event and clk='1') then
             if(tim3="0000" and tim4="0000") then
                tim3<="0000";
                tim4<="0100";
                next_state2<=s0;
             elsif(tim4="0000") then
                tim3<=tim3-1;
                tim4<="1001";
                next_state2<=s2;
             else
                tim4<=tim4-1;
                next_state2<=s2;
             end if;
          end if;
end case;
end process;
time1<=tim1;
time2<=tim2;
time3<=tim3;
time4<=tim4;
end arch;