📄 top.map.rpt
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+-------------------------------------------------------------------+
; State Machine - |controller|next_state1 ;
+----------------+----------------+----------------+----------------+
; Name ; next_state1.s2 ; next_state1.s1 ; next_state1.s0 ;
+----------------+----------------+----------------+----------------+
; next_state1.s0 ; 0 ; 0 ; 0 ;
; next_state1.s1 ; 0 ; 1 ; 1 ;
; next_state1.s2 ; 1 ; 0 ; 1 ;
+----------------+----------------+----------------+----------------+
+-------------------------------------------------------------------+
; State Machine - |controller|fsm71 ;
+----------------+----------------+----------------+----------------+
; Name ; next_state2_74 ; next_state2_72 ; next_state2_69 ;
+----------------+----------------+----------------+----------------+
; next_state2_69 ; 0 ; 0 ; 0 ;
; next_state2_72 ; 0 ; 1 ; 1 ;
; next_state2_74 ; 1 ; 0 ; 1 ;
+----------------+----------------+----------------+----------------+
+-------------------------------------------------------------------+
; State Machine - |controller|fsm94 ;
+----------------+----------------+----------------+----------------+
; Name ; next_state2_97 ; next_state2_95 ; next_state2_92 ;
+----------------+----------------+----------------+----------------+
; next_state2_92 ; 0 ; 0 ; 0 ;
; next_state2_95 ; 0 ; 1 ; 1 ;
; next_state2_97 ; 1 ; 0 ; 1 ;
+----------------+----------------+----------------+----------------+
+-------------------------------------------------------------------+
; State Machine - |controller|next_state2 ;
+----------------+----------------+----------------+----------------+
; Name ; next_state2.s2 ; next_state2.s1 ; next_state2.s0 ;
+----------------+----------------+----------------+----------------+
; next_state2.s0 ; 0 ; 0 ; 0 ;
; next_state2.s1 ; 0 ; 1 ; 1 ;
; next_state2.s2 ; 1 ; 0 ; 1 ;
+----------------+----------------+----------------+----------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 44 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 2 ;
; Number of registers using Asynchronous Clear ; 6 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 6 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |controller|tim1~11 ;
; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |controller|tim3~11 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/traffic_controller/top.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Aug 16 14:44:34 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Info: Found 2 design units, including 1 entities, in source file controller.vhd
Info: Found design unit 1: controller-arch
Info: Found entity 1: controller
Info: Elaborating entity "controller" for the top level hierarchy
Info: Duplicate registers merged to single register
Info: Duplicate register "tim1~12" merged to single register "tim1~0"
Info: Duplicate register "tim1[3]" merged to single register "tim1~0"
Info: Duplicate register "tim1~14" merged to single register "tim1~9"
Info: Duplicate register "tim1[2]" merged to single register "tim1~9"
Info: Duplicate register "tim1[1]" merged to single register "tim1~10"
Info: Duplicate register "tim1~16" merged to single register "tim1~11"
Info: Duplicate register "tim1[0]" merged to single register "tim1~11"
Info: Duplicate register "tim2~12" merged to single register "tim2~8"
Info: Duplicate register "tim2~13" merged to single register "tim2~9"
Info: Duplicate register "tim2~14" merged to single register "tim2~10"
Info: Duplicate register "tim2[1]" merged to single register "tim2~10"
Info: Duplicate register "tim2~15" merged to single register "tim2~11"
Info: Duplicate register "tim3~12" merged to single register "tim3~0"
Info: Duplicate register "tim3[3]" merged to single register "tim3~0"
Info: Duplicate register "tim3~13" merged to single register "tim3~9"
Info: Duplicate register "tim3[2]" merged to single register "tim3~9"
Info: Duplicate register "tim3~14" merged to single register "tim3~10"
Info: Duplicate register "tim3~15" merged to single register "tim3~11"
Info: Duplicate register "tim3[0]" merged to single register "tim3~11"
Info: Duplicate register "tim4~17" merged to single register "tim4~10"
Info: Duplicate register "tim4[1]" merged to single register "tim4~10"
Info: Duplicate register "tim4[3]" merged to single register "tim4~15"
Info: Duplicate register "tim4[2]" merged to single register "tim4~16"
Info: Duplicate register "tim4[0]" merged to single register "tim4~18"
Info: State machine "|controller|pre_state1" contains 3 states and 0 state bits
Info: State machine "|controller|pre_state2" contains 3 states and 0 state bits
Info: State machine "|controller|fsm19" contains 3 states and 0 state bits
Info: State machine "|controller|fsm48" contains 3 states and 0 state bits
Info: State machine "|controller|next_state1" contains 3 states and 0 state bits
Info: State machine "|controller|fsm71" contains 3 states and 0 state bits
Info: State machine "|controller|fsm94" contains 3 states and 0 state bits
Info: State machine "|controller|next_state2" contains 3 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|controller|pre_state1"
Info: Encoding result for state machine "|controller|pre_state1"
Info: Completed encoding using 3 state bits
Info: Encoded state bit "pre_state1.s2"
Info: Encoded state bit "pre_state1.s1"
Info: Encoded state bit "pre_state1.s0"
Info: State "|controller|pre_state1.s0" uses code string "000"
Info: State "|controller|pre_state1.s1" uses code string "011"
Info: State "|controller|pre_state1.s2" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|controller|pre_state2"
Info: Encoding result for state machine "|controller|pre_state2"
Info: Completed encoding using 3 state bits
Info: Encoded state bit "pre_state2.s2"
Info: Encoded state bit "pre_state2.s1"
Info: Encoded state bit "pre_state2.s0"
Info: State "|controller|pre_state2.s0" uses code string "000"
Info: State "|controller|pre_state2.s1" uses code string "011"
Info: State "|controller|pre_state2.s2" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|controller|fsm19"
Info: Encoding result for state machine "|controller|fsm19"
Info: Completed encoding using 3 state bits
Info: Encoded state bit "next_state1_22"
Info: Encoded state bit "next_state1_20"
Info: Encoded state bit "next_state1_17"
Info: State "|controller|next_state1_17" uses code string "000"
Info: State "|controller|next_state1_20" uses code string "011"
Info: State "|controller|next_state1_22" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|controller|fsm48"
Info: Encoding result for state machine "|controller|fsm48"
Info: Completed encoding using 3 state bits
Info: Encoded state bit "next_state1_51"
Info: Encoded state bit "next_state1_49"
Info: Encoded state bit "next_state1_138"
Info: State "|controller|next_state1_138" uses code string "000"
Info: State "|controller|next_state1_49" uses code string "011"
Info: State "|controller|next_state1_51" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|controller|next_state1"
Info: Encoding result for state machine "|controller|next_state1"
Info: Completed encoding using 3 state bits
Info: Encoded state bit "next_state1.s2"
Info: Encoded state bit "next_state1.s1"
Info: Encoded state bit "next_state1.s0"
Info: State "|controller|next_state1.s0" uses code string "000"
Info: State "|controller|next_state1.s1" uses code string "011"
Info: State "|controller|next_state1.s2" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|controller|fsm71"
Info: Encoding result for state machine "|controller|fsm71"
Info: Completed encoding using 3 state bits
Info: Encoded state bit "next_state2_74"
Info: Encoded state bit "next_state2_72"
Info: Encoded state bit "next_state2_69"
Info: State "|controller|next_state2_69" uses code string "000"
Info: State "|controller|next_state2_72" uses code string "011"
Info: State "|controller|next_state2_74" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|controller|fsm94"
Info: Encoding result for state machine "|controller|fsm94"
Info: Completed encoding using 3 state bits
Info: Encoded state bit "next_state2_97"
Info: Encoded state bit "next_state2_95"
Info: Encoded state bit "next_state2_92"
Info: State "|controller|next_state2_92" uses code string "000"
Info: State "|controller|next_state2_95" uses code string "011"
Info: State "|controller|next_state2_97" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|controller|next_state2"
Info: Encoding result for state machine "|controller|next_state2"
Info: Completed encoding using 3 state bits
Info: Encoded state bit "next_state2.s2"
Info: Encoded state bit "next_state2.s1"
Info: Encoded state bit "next_state2.s0"
Info: State "|controller|next_state2.s0" uses code string "000"
Info: State "|controller|next_state2.s1" uses code string "011"
Info: State "|controller|next_state2.s2" uses code string "101"
Info: Implemented 86 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 22 output pins
Info: Implemented 62 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Aug 16 14:44:38 2006
Info: Elapsed time: 00:00:05
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