tool.fit.qmsg

这是使用VHDL语言编写的密码锁程序,供大家参考

{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 41 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  41 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 42 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 45 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 42 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.196 ns memory register " "Info: Estimated most critical path is memory to register delay of 7.196 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns decoder:u1\|altsyncram:reduce_or_rtl_1\|altsyncram_b1j:auto_generated\|ram_block1a1~porta_address_reg0 1 MEM M4K_X33_Y19 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y19; Fanout = 1; MEM Node = 'decoder:u1\|altsyncram:reduce_or_rtl_1\|altsyncram_b1j:auto_generated\|ram_block1a1~porta_address_reg0'" {  } { { "E:/password_lock/db/tool_cmp.qrpt" "" { Report "E:/password_lock/db/tool_cmp.qrpt" Compiler "tool" "UNKNOWN" "V1" "E:/password_lock/db/tool.quartus_db" { Floorplan "E:/password_lock/" "" "" { decoder:u1|altsyncram:reduce_or_rtl_1|altsyncram_b1j:auto_generated|ram_block1a1~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_b1j.tdf" "" { Text "E:/password_lock/db/altsyncram_b1j.tdf" 59 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns decoder:u1\|altsyncram:reduce_or_rtl_1\|altsyncram_b1j:auto_generated\|q_a\[1\] 2 MEM M4K_X33_Y19 2 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X33_Y19; Fanout = 2; MEM Node = 'decoder:u1\|altsyncram:reduce_or_rtl_1\|altsyncram_b1j:auto_generated\|q_a\[1\]'" {  } { { "E:/password_lock/db/tool_cmp.qrpt" "" { Report "E:/password_lock/db/tool_cmp.qrpt" Compiler "tool" "UNKNOWN" "V1" "E:/password_lock/db/tool.quartus_db" { Floorplan "E:/password_lock/" "" "4.308 ns" { decoder:u1|altsyncram:reduce_or_rtl_1|altsyncram_b1j:auto_generated|ram_block1a1~porta_address_reg0 decoder:u1|altsyncram:reduce_or_rtl_1|altsyncram_b1j:auto_generated|q_a[1] } "NODE_NAME" } "" } } { "db/altsyncram_b1j.tdf" "" { Text "E:/password_lock/db/altsyncram_b1j.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.298 ns) + CELL(0.114 ns) 5.720 ns process0~73 3 COMB LAB_X35_Y15 1 " "Info: 3: + IC(1.298 ns) + CELL(0.114 ns) = 5.720 ns; Loc. = LAB_X35_Y15; Fanout = 1; COMB Node = 'process0~73'" {  } { { "E:/password_lock/db/tool_cmp.qrpt" "" { Report "E:/password_lock/db/tool_cmp.qrpt" Compiler "tool" "UNKNOWN" "V1" "E:/password_lock/db/tool.quartus_db" { Floorplan "E:/password_lock/" "" "1.412 ns" { decoder:u1|altsyncram:reduce_or_rtl_1|altsyncram_b1j:auto_generated|q_a[1] process0~73 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.292 ns) 6.384 ns process0~75 4 COMB LAB_X35_Y15 1 " "Info: 4: + IC(0.372 ns) + CELL(0.292 ns) = 6.384 ns; Loc. = LAB_X35_Y15; Fanout = 1; COMB Node = 'process0~75'" {  } { { "E:/password_lock/db/tool_cmp.qrpt" "" { Report "E:/password_lock/db/tool_cmp.qrpt" Compiler "tool" "UNKNOWN" "V1" "E:/password_lock/db/tool.quartus_db" { Floorplan "E:/password_lock/" "" "0.664 ns" { process0~73 process0~75 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.738 ns) 7.196 ns lockopen~reg0 5 REG LAB_X35_Y15 2 " "Info: 5: + IC(0.074 ns) + CELL(0.738 ns) = 7.196 ns; Loc. = LAB_X35_Y15; Fanout = 2; REG Node = 'lockopen~reg0'" {  } { { "E:/password_lock/db/tool_cmp.qrpt" "" { Report "E:/password_lock/db/tool_cmp.qrpt" Compiler "tool" "UNKNOWN" "V1" "E:/password_lock/db/tool.quartus_db" { Floorplan "E:/password_lock/" "" "0.812 ns" { process0~75 lockopen~reg0 } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "E:/password_lock/lock.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.452 ns 75.76 % " "Info: Total cell delay = 5.452 ns ( 75.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.744 ns 24.24 % " "Info: Total interconnect delay = 1.744 ns ( 24.24 % )" {  } {  } 0}  } { { "E:/password_lock/db/tool_cmp.qrpt" "" { Report "E:/password_lock/db/tool_cmp.qrpt" Compiler "tool" "UNKNOWN" "V1" "E:/password_lock/db/tool.quartus_db" { Floorplan "E:/password_lock/" "" "7.196 ns" { decoder:u1|altsyncram:reduce_or_rtl_1|altsyncram_b1j:auto_generated|ram_block1a1~porta_address_reg0 decoder:u1|altsyncram:reduce_or_rtl_1|altsyncram_b1j:auto_generated|q_a[1] process0~73 process0~75 lockopen~reg0 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}